Abstract: A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.

Abstract: A semiconductor device including a chip stack structure having a plurality of semiconductor chips, the semiconductor chips being stacked such that they are electrically connected using through-electrodes, and a support frame attached to a side surface of the chip stack structure.

Abstract: A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal.

Abstract: A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.

Abstract: A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.

Abstract: A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner.

Abstract: A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.

Abstract: A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal.

Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.

Abstract: A semiconductor device including a chip stack structure having a plurality of semiconductor chips, the semiconductor chips being stacked such that they are electrically connected using through-electrodes, and a support frame attached to a side surface of the chip stack structure.

Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.

Abstract: A semiconductor package including a first semiconductor package including a first terminal and a second terminal provided on a surface different from a surface on which the first terminal is formed, and a second semiconductor package including a third terminal connected to the first terminal, wherein the surface on which the first terminal is formed faces a surface on which the third terminal is formed.

Abstract: A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.

Abstract: A mobile terminal is presented. The mobile terminal includes a memory unit, a wireless communication unit, a touchscreen configured to display a webpage including at least one hyperlink, and a controller configured to store a hyperlink selected on the touchscreen in the memory unit, display information associated with the selected hyperlink on the touchscreen, and display, on the touchscreen, a webpage linked to the selected hyperlink when the displayed information is selected.

Abstract: The invention relates to a method for manufacturing dielectric ceramic powder and a multilayer ceramic capacitor using the ceramic powder. According to the invention, BaCO3 powder is dispersed into a solution of solvent and dispersant to prepare BaCO3 slurry and then the resultant BaCO3 slurry is wet-milled. Also, TiO2 powder slurry is mixed into the wet-milled BaCO3 slurry to form mixed slurry and then the mixed slurry is dried into mixed powder. Finally, the dried mixed powder is calcined to produce BaTiO3 powder.

Abstract: The invention relates to a method for manufacturing dielectric ceramic powder and a multilayer ceramic capacitor using the ceramic powder. According to the invention, BaCO3 powder is dispersed into a solution of solvent and dispersant to prepare BaCO3 slurry and then the resultant BaCO3 slurry is wet-milled. Also, TiO2 powder slurry is mixed into the wet-milled BaCO3 slurry to form mixed slurry and then the mixed slurry is dried into mixed powder. Finally, the dried mixed powder is calcined to produce BaTiO3 powder.