Patents by Inventor Sung-Un Kwon
Sung-Un Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8158445Abstract: Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.Type: GrantFiled: November 5, 2010Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hwan Ryu, Jae-Seung Hwang, Sung-Un Kwon, Kyoung-Ha Eom
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Patent number: 8133757Abstract: A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.Type: GrantFiled: December 3, 2009Date of Patent: March 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Kwon, Young-Soo Lim, Sung-Un Kwon, Yong-Ho Ha, Jeong-Hee Park, Joon-Sang Park, Myung-Jin Kang, Doo-Hwan Park
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Publication number: 20120040508Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.Type: ApplicationFiled: July 22, 2011Publication date: February 16, 2012Inventors: Gyu-Hwan Oh, Sung-Lae Cho, Byoung-Jae Bae, Ik-Soo Kim, Dong-Hyun Im, Doo-Hwan Park, Kyoung-Ha Eom, Sung-Un Kwon, Chul-Ho Shin, Sang-Sup Jeong
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Publication number: 20110281428Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.Type: ApplicationFiled: July 15, 2011Publication date: November 17, 2011Inventors: Yong-Hwan Ryu, Jun Seo, Eun-Young Kang, Jae-Seung Hwang, Sung-Un Kwon
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Patent number: 7989279Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.Type: GrantFiled: June 10, 2008Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hwan Ryu, Jun Seo, Eun-Young Kang, Jae-Seung Hwang, Sung-Un Kwon
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Publication number: 20110111532Abstract: Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.Type: ApplicationFiled: November 5, 2010Publication date: May 12, 2011Inventors: Yong-Hwan RYU, Jae-Seung HWANG, Sung-Un KWON, Kyoung-Ha EOM
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Patent number: 7777265Abstract: A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.Type: GrantFiled: October 31, 2007Date of Patent: August 17, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeong-Sun Hong, Jae-Goo Lee, Dong-Hyun Kim, Sung-Un Kwon, Sang-Joon Park, Nam-Jung Kang
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Publication number: 20100144135Abstract: A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.Type: ApplicationFiled: December 3, 2009Publication date: June 10, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Suk Kwon, Young-Soo Lim, Sung-Un Kwon, Yong-Ho Ha, Jeong-Hee Park, Joon-Sang Park, Myung-Jin Kang, Doo-Hwan Park
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Patent number: 7659162Abstract: A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.Type: GrantFiled: October 8, 2008Date of Patent: February 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Soo Lim, Yong-Sun Ko, Sung-Un Kwon, Jae-Seung Hwang
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Patent number: 7531450Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.Type: GrantFiled: June 7, 2007Date of Patent: May 12, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-Seung Kang, Jun Seo, Min-Chul Chae, Jae-Seung Hwang, Sung-Un Kwon, Woo-Jin Cho
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Publication number: 20090090899Abstract: A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.Type: ApplicationFiled: October 8, 2008Publication date: April 9, 2009Inventors: Young-Soo Lim, Yong-Sun Ko, Sung-Un Kwon, Jae-Seung Hwang
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Patent number: 7498253Abstract: A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern.Type: GrantFiled: February 27, 2007Date of Patent: March 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Un Kwon, Yong-Sun Ko
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Publication number: 20090020816Abstract: One embodiment generally described herein can be characterized as a semiconductor device. The semiconductor device can include a first transistor on a semiconductor substrate. A first interlayer insulating layer may be disposed over the first transistor and includes a first recess region. A single-crystalline semiconductor pattern may be disposed in the first recess region. A single-crystalline semiconductor plug may connect the semiconductor substrate to the single-crystalline semiconductor pattern. A second transistor may be disposed on the single-crystalline semiconductor pattern.Type: ApplicationFiled: July 17, 2008Publication date: January 22, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo-Jin CHO, Yong-Woo LEE, Jae-Seung HWANG, Sung-Un KWON, Min-Chul CHAE
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Publication number: 20090011590Abstract: A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.Type: ApplicationFiled: June 10, 2008Publication date: January 8, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hwan RYU, Jun SEO, Eun-Young KANG, Jae-Seung HWANG, Sung-Un KWON
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Patent number: 7452773Abstract: In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.Type: GrantFiled: June 9, 2006Date of Patent: November 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Un Kwon, Yong-Sun Ko, Jae-Seung Hwang
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Publication number: 20080088029Abstract: A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.Type: ApplicationFiled: October 31, 2007Publication date: April 17, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyeong-Sun HONG, Jae-Goo LEE, Dong-Hyun KIM, Sung-Un KWON, Sang-Joon PARK, Nam-Jung KANG
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Publication number: 20070287287Abstract: Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.Type: ApplicationFiled: June 7, 2007Publication date: December 13, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-Seung KANG, Jun SEO, Min-Chul CHAE, Jae-Seung HWANG, Sung-Un KWON, Woo-Jin CHO
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Publication number: 20070141834Abstract: A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern.Type: ApplicationFiled: February 27, 2007Publication date: June 21, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Un KWON, Yong-Sun KO
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Patent number: 7202163Abstract: A Local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern.Type: GrantFiled: June 4, 2004Date of Patent: April 10, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Un Kwon, Yong-Sun Ko
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Publication number: 20070004140Abstract: In a method of manufacturing a non-volatile semiconductor memory device that includes a first region having a first gate structure and a second region having a second gate structure, the first gate structure may include a tunnel oxide layer pattern, a first conductive layer pattern, a dielectric layer pattern and a second conductive layer pattern. A first photoresist pattern may be formed on the second conductive layer pattern to form a source line which may be formed in a region of the first area by implanting impurities. A second photoresist pattern may be formed on a hard mask layer in the second region of the substrate to form a hard mask pattern on a third conductive layer. The second gate structure having substantially vertical sidewalls may be formed in the second area by etching the third conductive layer using the hard mask pattern.Type: ApplicationFiled: June 27, 2006Publication date: January 4, 2007Inventors: Dae-Hyun Jang, Jae-Seung Hwang, Dae-Youp Lee, Sung-Un Kwon