Patents by Inventor Sung-Wook Hwang
Sung-Wook Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10217742Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.Type: GrantFiled: February 22, 2018Date of Patent: February 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In Wook Oh, Jae Seok Yang, Jong Hyun Lee, Hyun Jae Lee, Sung Wook Hwang
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Publication number: 20190051600Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.Type: ApplicationFiled: January 17, 2018Publication date: February 14, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: In Wook OH, Dong Hyun KIM, Doo Hwan PARK, Sung Keun PARK, Chul Hong PARK, Sung Wook HWANG
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Patent number: 10204892Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.Type: GrantFiled: June 14, 2017Date of Patent: February 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
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Patent number: 10079172Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.Type: GrantFiled: September 13, 2017Date of Patent: September 18, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-Wook Oh, Jong-Hyun Lee, Sung-Wook Hwang
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Publication number: 20180248371Abstract: The present invention relates to an inverter device for a microgrid, and a method for controlling the same, the inverter device including: a waveform detector detecting a voltage waveform and a current waveform applied to a load; a control unit determining whether a sine wave appears based on the detected voltage waveform and the detected current waveform and performing voltage control or low order harmonic compensation depending on a determination result; and a switch generating a voltage waveform in a form of the sine wave by being turned on/off depending on a control signal received from the control unit and supplying the generated voltage waveform in the form of the sine wave to the load.Type: ApplicationFiled: July 14, 2016Publication date: August 30, 2018Inventors: Woo-Kyu CHAE, Hak-Ju LEE, Jong-Nam WON, Il-Keun SONG, Jung-Sung PARK, Sung-Wook HWANG
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Publication number: 20180182758Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.Type: ApplicationFiled: February 22, 2018Publication date: June 28, 2018Inventors: In Wook OH, Jae Seok YANG, Jong Hyun LEE, Hyun Jae LEE, Sung Wook HWANG
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INTEGRATED CONTROL METHOD FOR IMPROVING FORWARD COLLISION AVOIDANCE PERFORMANCE AND VEHICLE THEREFOR
Publication number: 20180162444Abstract: A vehicle according to an exemplary embodiment of the present invention includes an electronic chassis control system configured for an electronic control suspension (ECS), a motor driven power steering system (MDPS), an electronic stability control (ESC), and an all wheel drive (AWD), and an integrated controller implementing an integrated avoidance control in which controls for each of the MDPS, the ESC, and the AWD according to an emergency avoidance control of the ECS in the forward collision situation, wherein it is possible to safely and rapidly avoid risk of forward collision, and cooperative control performance of the ECS and the AWD, the ESC and the MDPS is optimized by applying an emergency grade to the integrated avoidance control.Type: ApplicationFiled: November 10, 2017Publication date: June 14, 2018Applicants: Hyundai Motor Company, Kia Motors CorporationInventors: Jae-II Park, Sung-Wook Hwang -
Publication number: 20180162335Abstract: A method of controlling driving of a vehicle using an in-wheel system includes determining whether the vehicle enters a steering avoidance section, based on driving information of the vehicle, verifying a detailed or specific section in the steering avoidance section in which the vehicle is located when the vehicle enters the steering avoidance section, and controlling torque of a motor mounted in each wheel to satisfy a yaw moment required in the verified detailed section.Type: ApplicationFiled: May 28, 2017Publication date: June 14, 2018Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATIONInventor: Sung Wook Hwang
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Patent number: 9928330Abstract: In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.Type: GrantFiled: June 11, 2015Date of Patent: March 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Kwon Kang, Ji-young Jung, Dong-Gyun Kim, Jae-Seok Yang, Sung-Wook Hwang
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Patent number: 9929156Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.Type: GrantFiled: December 8, 2016Date of Patent: March 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In Wook Oh, Jae Seok Yang, Jong Hyun Lee, Hyun Jae Lee, Sung Wook Hwang
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Patent number: 9874810Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.Type: GrantFiled: April 21, 2016Date of Patent: January 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Jung, Dae-Kwon Kang, Dong-Gyun Kim, Jae-Seok Yang, Sung-Wook Hwang
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Publication number: 20180012794Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.Type: ApplicationFiled: September 13, 2017Publication date: January 11, 2018Inventors: In-Wook Oh, Jong-Hyun Lee, Sung-Wook Hwang
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Patent number: 9847319Abstract: A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages.Type: GrantFiled: May 6, 2016Date of Patent: December 19, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Sub Song, Sung-Wook Hwang, Yeoung-Jun Cho, Ki-Hong Jeong, Tae-Heum Kim
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Publication number: 20170358564Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.Type: ApplicationFiled: June 14, 2017Publication date: December 14, 2017Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
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Patent number: 9841672Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.Type: GrantFiled: April 17, 2015Date of Patent: December 12, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Kwon Kang, Jae-Seok Yang, Sung-Wook Hwang, Dong-Gyun Kim, Ji-Young Jung
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Patent number: 9824916Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.Type: GrantFiled: August 29, 2016Date of Patent: November 21, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: In-Wook Oh, Jong-Hyun Lee, Sung-Wook Hwang
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Patent number: 9812356Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.Type: GrantFiled: January 13, 2017Date of Patent: November 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Wook Hwang, Jong Hyun Lee, Jae Seok Yang, In Wook Oh, Hyun Jae Lee
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Publication number: 20170287909Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.Type: ApplicationFiled: December 8, 2016Publication date: October 5, 2017Inventors: In Wook OH, Jae Seok YANG, Jong Hyun LEE, Hyun Jae LEE, Sung Wook HWANG
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Publication number: 20170271204Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.Type: ApplicationFiled: January 13, 2017Publication date: September 21, 2017Inventors: Sung Wook HWANG, Jong Hyun LEE, Jae Seok YANG, In Wook OH, Hyun Jae LEE
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Publication number: 20170169153Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.Type: ApplicationFiled: September 8, 2016Publication date: June 15, 2017Inventors: SUNG-WOOK HWANG, JONG-HYUN LEE, MIN-SOO KANG