Abstract: There is provided a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first gate stacked body including a first channel hole, a second gate stacked body overlapping the first gate stacked body and including a second channel hole, a first memory layer extending along an inner wall of the first channel hole, a second memory layer extending along an inner wall of the second channel hole and including an end protruding into the first channel hole.

Abstract: A glenoid baseplate and, more specifically, to a glenoid baseplate of an artificial shoulder joint, includes: a base which is mounted on the glenoid fossa of the scapula and has a first surface; an augment disposed on the first surface; and a stem extended from the first surface while having a center axis, wherein one surface of the augment forms a contact surface with the first surface, at least a portion of the contact surface forms a predetermined angle, that is not a right angle, with respect to the center axis of the stem, and the augment includes a first wedge having a second surface extended from a first boundary and a second wedge having a third surface bent and extended from the second surface, and thus the present invention compensates for bone defects, minimizes bone cutting, and has a simple shape so as to facilitate manufacturing.

Abstract: The present technology relates to a semiconductor device, a method of manufacturing the same, and a method of operating the same. The semiconductor device includes a gate stack including first interlayer insulating layers and word line stack layers alternately stacked, a vertical channel structure extending in a vertical direction in the gate stack, and memory structures interposed between the word line stack layers and the vertical channel structure, each of the word line stack layers includes an even conductive layer, a second interlayer insulating layer, and an odd conductive layer sequentially stacked, and a thickness of any one of the first interlayer insulating layers is greater than a thickness of any one of the second interlayer insulating layers.

Abstract: Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a transistor, a cell array structure, a molded insulating structure including a first area disposed between the transistor and the cell array structure and overlapping with the transistor and a second area extending sideways from the first area, a pass gate disposed in the second area of the molded insulating structure, an active pillar penetrating the pass gate, and a pass gate insulating layer disposed between the active pillar and the pass gate.

Abstract: There is provided a semiconductor memory device. The semiconductor memory device includes a first peripheral circuit structure, a cell array structure, a mold insulating structure disposed between the first peripheral circuit structure and the cell array structure, and a second peripheral circuit structure disposed in the mold insulating structure and including a pass transistor.

Abstract: A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.

Abstract: There are provided a semiconductor device and a manufacturing method of a semiconductor device. The semiconductor device includes: a gate stack structure including interlayer insulating layers and conductive layers, which are alternately stacked; a channel structure extending in a vertical direction in the gate stack structure; and memory structures interposed between the conductive layers and the channel structure. Each of the memory structures includes a blocking insulating layer and a charge trap layer, which are sequentially formed on a sidewall of each of the conductive layers. Sidewalls of the interlayer insulating layers, which are in contact with the channel structure, are located on the same line as a sidewall of the charge trap layer, which is in contact with the channel structure, or side portions of the interlayer insulating layers, which are in contact with the channel structure, further protrude as compared with the sidewall of the charge trap layer.

Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.

Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.

Abstract: A glenoid baseplate and, more specifically, to a glenoid baseplate of an artificial shoulder joint, includes: a base seated on the glenoid cavity of the scapula; an augment formed on one surface of the base; and a stem extending from the base to one side while having a central axis, wherein the augment comprises a plate having a second surface extending from one end of the plate in one direction. The plate extends from one end of the base through the central axis to a point spaced apart by a first length from the central axis, and the wedge extends from one end of the plate in a first direction such that the thickness thereof gradually decreases. Accordingly, it is possible to minimize bone cutting and correct an insertion axis of the baseplate.

Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.

Abstract: Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a gate stacked body in which a plurality of interlayer insulating layers and a plurality of conductive patterns are alternately stacked, and a plurality of channel structures disposed to extend in a vertical direction in the gate stacked body disposed in a cell region, wherein the plurality of conductive patterns extend in a horizontal direction in the cell region, and extend in the vertical direction or in a direction between the vertical direction and the horizontal direction in a word line contact region adjacent to the cell region.

Abstract: There is provided a data interworking method between a oneM2M system and an NGSI-LD system. The data interworking method according to an embodiment of the present disclosure includes: retrieving, by an IPE, resources in the oneM2M system that perform data interworking with the NGSI-LD system; retrieving labels of the retrieved resources; acquiring a mapping-rule from the retrieved labels; and storing the acquired mapping-rule. Accordingly, data interworking between data platforms using different standards is performed more easily, so that technology may go one step further to the goal of interconnecting and servicing all things in a global environment as IoT ultimately pursues.

Abstract: A semiconductor device may include: a first semiconductor structure including a stack including an inverted step structure, a source structure located below the stack, a bit line located above the stack, and channel structures extending through the stack; a second semiconductor structure bonded to the first semiconductor structure and including pass transistors located to face the inverted step structure and a first peripheral circuit located to face the source structure; and a third semiconductor structure bonded to the first semiconductor structure and including a page buffer located to face the bit line and a second peripheral circuit located to face the inverted step structure.

Abstract: A semiconductor device may include: first semiconductor structure including a page buffer, a first peripheral circuit, a bit line located on the page buffer, a stack located on the bit line and the stack including a) a step structure, b) a source structure located on the stack, and channel structures extending through the stack; and a second semiconductor structure bonded to the first semiconductor structure and the second semiconductor structure including a) a second peripheral circuit located to face the source structure and b) pass transistors located to face the step structure.

Abstract: A semiconductor device may include a gate structure including conductive layers and insulating layers that are alternately stacked and including a stair structure for exposing at least one of the conductive layers, a contact plug that extends through the gate structure and that is electrically connected to a uppermost conductive layer that is exposed by the stair structure, and insulating spacers that are disposed between remaining conductive layers, among the conductive layers, and the contact plug. The insulating layers may each have a first thickness, and the insulating spacers may each have a second thickness smaller than the first thickness.

Abstract: A semiconductor memory device includes a memory cell array (MCA) and a pass transistor unit (PTU). The MCA includes memory block(s) that has source selection line(s) (SSL), word lines (WLs), drain selection line(s) (DSL), and dummy WL(s) (DWL). The PTU includes source pass transistor(s) to selectively transmit a source driving signal (source DS) to the SSL, memory pass transistors (MPTs) to selectively transmit a WL DS to the WLs, respectively, drain pass transistor(s) (PT) to selectively transmit a drain DS to the DSL, and dummy PT(s) to selectively transmit a DWL DS to the DWL. The source DS, the WL DS, the drain DS, and the DWL DS may each be associated with a respective voltage range. Sizes of the source PT, the MPTs, the drain PT, and the dummy PTs are set based on the respective voltage ranges.

Abstract: A semiconductor device includes a gate structure including a cell region and a contact region, a slit structure configured to extend in a first direction through the gate structure, first channel structures disposed in the cell region of the gate structure, and second channel structures disposed in the cell region of the gate structure and disposed to be more adjacent to the contact region of the gate structure than the first channel structures. In a second direction that intersects the first direction, the first channel structures may be spaced apart from the slit structure by a first distance, and the second channel structures may be spaced apart from the slit structure at a second distance.

Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device includes a first select line and a second select line disposed with a slit interposed therebetween, and a channel structure that is disposed in each of the first select line and the second select line and is adjacent to the slit. In the semiconductor memory device, the channel structure includes a sidewall facing the slit.

Abstract: There is provided a data interworking method between a oneM2M system and an NGSI-LD system. The data interworking method according to an embodiment of the present disclosure includes: retrieving, by an IPE, resources in the oneM2M system that perform data interworking with the NGSI-LD system; retrieving labels of the retrieved resources; acquiring a mapping-rule from the retrieved labels; and storing the acquired mapping-rule. Accordingly, data interworking between data platforms using different standards is performed more easily, so that technology may go one step further to the goal of interconnecting and servicing all things in a global environment as IoT ultimately pursues.