Patents by Inventor Sung Wook Jung

Sung Wook Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240032296
    Abstract: A semiconductor memory device includes: a gate stack structure including a plurality of conductive patterns; a channel structure disposed inside the gate stack structure, the channel structure having a cross-sectional structure including a major axis and a minor axis, which faces in directions intersecting each other; and two or more bit lines extending in a direction intersecting the major axis of the channel structure, the two or more bit lines being arranged to be spaced apart from each other in a direction in which the major axis of the channel structure faces.
    Type: Application
    Filed: January 20, 2023
    Publication date: January 25, 2024
    Applicant: SK hynix Inc.
    Inventor: Sung Wook JUNG
  • Publication number: 20230337433
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 19, 2023
    Applicant: SK hynix Inc.
    Inventor: Sung Wook JUNG
  • Publication number: 20230301098
    Abstract: A three-dimensional (3D) semiconductor device includes a plurality of stack structures, a plurality of channel plugs, a slit structure and a plurality of dummy channel plugs. The stack structures include at least two conductive layers and at least two insulation layers, each being alternately stacked. The channel plugs are vertically formed through the stack structure. The slit structure is arranged at one side of the stack structure. The plurality of dummy channel plugs is arranged in the stack structures to be adjacent to the slit structure. Each of the channel plugs includes a channel insulation layer and a channel layer. Each of the dummy channel plugs includes at least one of the channel insulation layer, the channel layer, and a material of the plurality of conductive layers.
    Type: Application
    Filed: October 25, 2022
    Publication date: September 21, 2023
    Applicant: SK hynix Inc.
    Inventor: Sung Wook JUNG
  • Publication number: 20230301091
    Abstract: There are provided a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a plurality of channel structures penetrating the gate structure, the plurality of channel structures being arranged in a first direction; a plurality of cutting structures each isolating each of the plurality of channel structures, respectively, into a plurality of divided channel structures while penetrating each of the plurality of channel structures, respectively; and a plurality of interconnection lines located over the gate structure and extending in the first direction. Each of the plurality of cutting structures has substantially a cross (+) shape including extension parts extending in directions oblique to the first direction.
    Type: Application
    Filed: August 19, 2022
    Publication date: September 21, 2023
    Applicant: SK hynix Inc.
    Inventors: Sung Wook JUNG, Ji Hui BAEK, Jang Hee JUNG
  • Publication number: 20230262982
    Abstract: A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Applicant: SK hynix Inc.
    Inventor: Sung Wook JUNG
  • Patent number: 11723205
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: August 8, 2023
    Assignee: SK hynix Inc.
    Inventor: Sung Wook Jung
  • Publication number: 20230247823
    Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area defined by a periphery of the cell area, the cell area including a dummy cell area and a normal cell area, and an active area defined by a cell element isolation film. The device includes a cell area separation film defining the cell area in the substrate, the dummy cell area defining a boundary with the cell area separation film between the normal cell area and the cell area separation film. The device includes a normal bit-line on the normal cell area and extending in a first direction, a dummy bit-line group on the dummy cell area, the dummy bit-line group including a plurality of dummy bit-lines extending in the first direction, and a plurality of storage contacts connected to the active area and located along a second direction perpendicular to the first direction.
    Type: Application
    Filed: November 16, 2022
    Publication date: August 3, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seongkeun CHO, Jae Seong Park, Youngseok Kim, Young Sin Kim, Daeyoung Moon, Keum Joo Lee, Sung-Wook Jung, Sungduk Hong, Suhwan Hwang
  • Patent number: 11672122
    Abstract: A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: June 6, 2023
    Assignee: SK hynix Inc.
    Inventor: Sung Wook Jung
  • Publication number: 20230130743
    Abstract: Proposed is an artificial ankle joint bearing element in which a contact area of the bearing element with a talus element is increased such that stress is evenly distributed during bearing movement of the bearing element on the talus element and wear of the bearing element is reduced under the same load; the bearing element has a front and a rear convexly formed to increase a contact area with a tibial element and distribute stress; and the front and rear of the bearing element are asymmetrically formed such that the rear thereof is formed to have a smaller height than the front thereof so as to facilitate the insertion of the bearing element into space between the talus element and the tibial element from an anterior side thereof during artificial ankle joint surgery.
    Type: Application
    Filed: March 9, 2021
    Publication date: April 27, 2023
    Inventors: Keun-Bae Lee, Jea-Won Kim, Sung-Wook Jung
  • Publication number: 20230093758
    Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Inventors: Go Hyun LEE, Sung Wook JUNG
  • Publication number: 20230070775
    Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Inventors: Kang Bin YI, Dong Rak KO, Sung Ho KIM, Eun Ji SEO, Sung Hun SON, Hee Kyun SHIN, Seok Lyul YOON, Jeong Seok LEE, Sung Wook JUNG, Hwan Kyeong JEONG
  • Patent number: 11538821
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: December 27, 2022
    Assignee: SK hynix Inc.
    Inventors: Go Hyun Lee, Sung Wook Jung
  • Patent number: 11526039
    Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: December 13, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kang Bin Yi, Dong Rak Ko, Sung Ho Kim, Eun Ji Seo, Sung Hun Son, Hee Kyun Shin, Seok Lyul Yoon, Jeong Seok Lee, Sung Wook Jung, Hwan Kyeong Jeong
  • Patent number: 11501987
    Abstract: A semiconductor manufacturing apparatus includes a loadlock module including a loadlock chamber in which a substrate container is received, wherein the loadlock module is configured to switch an internal pressure of the loadlock chamber between atmospheric pressure and a vacuum; and a transfer module configured to transfer a substrate between the substrate container received in the loadlock chamber and a process module for performing a semiconductor manufacturing process on the substrate, wherein the loadlock module includes a purge gas supply unit configured to supply a purge gas into the substrate container through a gas supply line connected to the substrate container; and an exhaust unit configured to discharge a gas in the substrate container through an exhaust line connected to the substrate container.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-nam Kim, Byeong-Hee Kim, Jeongryul Kim, Hae-Joong Park, Jong-Woo Sun, Sang-Rok Oh, Sung-Wook Jung, Nam-Young Cho, Jung-Pyo Hong
  • Patent number: 11495611
    Abstract: A semiconductor memory device includes an electrode structure including a plurality of gate conductive films stacked on a substrate and a channel array in which a plurality of channel columns passing through the electrode structure are arranged in a second direction. The plurality of channel columns may include a first column whose uppermost plane has a first shape and a second column whose uppermost plane has a second shape. N (N is a natural number equal to more than 1) first columns and N second columns are alternately arranged in a first direction different from the second direction.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Wook Jung, Jang Hee Jung
  • Publication number: 20220336495
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: SK hynix Inc.
    Inventor: Sung Wook JUNG
  • Publication number: 20220283454
    Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Kang Bin YI, Dong Rak KO, Sung Ho KIM, Eun Ji SEO, Sung Hun SON, Hee Kyun SHIN, Seok Lyul YOON, Jeong Seok LEE, Sung Wook JUNG, Hwan Kyeong JEONG
  • Patent number: 11417680
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes a first select group and a second select group isolated from each other by an isolation insulating layer; an upper gate stack structure extending to overlap with the first select group, the isolation insulating layer, and the second select group; channel structures extending to penetrate the first select group, the second select group, and the upper gate stack structure; and a vertical connection structure spaced apart from the first select group, the second select group, and the upper gate stack structure, the vertical connection structure extending in parallel to the channel structures.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 16, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Wook Jung
  • Publication number: 20220238544
    Abstract: A semiconductor memory device includes a memory cell array (MCA) and a pass transistor unit (PTU). The MCA includes memory block(s) that has source selection line(s) (SSL), word lines (WLs), drain selection line(s) (DSL), and dummy WL(s) (DWL). The PTU includes source pass transistor(s) to selectively transmit a source driving signal (source DS) to the SSL, memory pass transistors (MPTs) to selectively transmit a WL DS to the WLs, respectively, drain pass transistor(s) (PT) to selectively transmit a drain DS to the DSL, and dummy PT(s) to selectively transmit a DWL DS to the DWL. The source DS, the WL DS, the drain DS, and the DWL DS may each be associated with a respective voltage range. Sizes of the source PT, the MPTs, the drain PT, and the dummy PTs are set based on the respective voltage ranges.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Applicant: SK hynix Inc.
    Inventor: Sung Wook JUNG
  • Patent number: 11340483
    Abstract: A display device includes first and second substrates each including a short side and a long side, ground parts located on at least one of the short and long sides of each of the first and second substrates and including at least one first ground surfaces, which are perpendicular to opposing surfaces of the first and second substrates, and at least one second ground surfaces, which are provided at at least one edge of the second substrate to define an obtuse angle with reference to the first ground surfaces, and unevenness disposed on the first ground surfaces along a first direction, where the unevenness defines an acute angle with reference to a normal line to the opposing surfaces.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kang Bin Yi, Dong Rak Ko, Sung Ho Kim, Eun Ji Seo, Sung Hun Son, Hee Kyun Shin, Seok Lyul Yoon, Jeong Seok Lee, Sung Wook Jung, Hwan Kyeong Jeong