Abstract: The present invention relates to a method for producing a super-hydrophobic surface, and to a stack having a super-hydrophobic surface prepared by the above method. The super-hydrophobic surface may be realized only by plasma etching and deposition. The super-hydrophobic surface according to the present invention has a very low work of adhesion less than or equal to 3 mJ/m2. This super-hydrophobic surface may be applied to various fields including self-cleaning surface, anti-fogging surface, automobile glass surface, and drug delivery device surface.

Abstract: There is provided a method for etching a silicon substrate, the method comprising: forming an etch mask on a silicon substrate; forming a first gas comprising a halogen-based gas, a fluorocarbon gas and oxygen; and etching the silicon substrate by generating a plasma on the silicon substrate using the first gas.

Abstract: The present invention provides a method for fabricating slanted copper nanorods. The method includes manufacturing a workpiece configured to include an etch stop layer on a wafer, placing the workpiece in a slanted position, and etching the slanted workpiece, forming a copper (Cu) layer on the slanted workpiece by plating, removing an over-plated portion from the copper layer, and removing a polysilicon (poly Si) excluding copper from the surface of the workpiece. According to the invention, copper nanorod structures having a uniform array can be fabricated in a large area at a high process yield compared to conventional methods. In addition, the angle and diameter of copper nanorods can be controlled as desired so that the applicability thereof can be greatly increased. Moreover, the present invention can be applied to processes for fabricating various devices, including semiconductor devices, MEMSs (microelectromechanical systems), optical devices, gas sensors, display devices, etc.

Abstract: The present invention provides a method for fabricating slanted copper nanorods. The method includes manufacturing a workpiece configured to include an etch stop layer on a wafer, placing the workpiece in a slanted position, and etching the slanted workpiece, forming a copper (Cu) layer on the slanted workpiece by plating, removing an over-plated portion from the copper layer, and removing a polysilicon (poly Si) excluding copper from the surface of the workpiece. According to the invention, copper nanorod structures having a uniform array can be fabricated in a large area at a high process yield compared to conventional methods. In addition, the angle and diameter of copper nanorods can be controlled as desired so that the applicability thereof can be greatly increased. Moreover, the present invention can be applied to processes for fabricating various devices, including semiconductor devices, MEMSs (microelectromechanical systems), optical devices, gas sensors, display devices, etc.

Abstract: This invention relates to a method of fabricating a three-dimensional copper nanostructure, including manufacturing a specimen configured to include a SiO2 mask; performing multi-directional slanted plasma etching to form a three-dimensional etching structure layer on the specimen; performing plating so that a multi-directional slanted plasma etched portion of the specimen is filled with a metal; removing an over-plated portion and the SiO2 mask from the metal layer; and removing a portion of a surface of the specimen other than the metal which is the three-dimensional etching structure layer.

Abstract: This invention relates to a method of fabricating a three-dimensional copper nanostructure, including manufacturing a specimen configured to include a SiO2 mask; performing multi-directional slanted plasma etching to form a three-dimensional etching structure layer on the specimen; performing plating so that a multi-directional slanted plasma etched portion of the specimen is filled with a metal; removing an over-plated portion and the SiO2 mask from the metal layer; and removing a portion of a surface of the specimen other than the metal which is the three-dimensional etching structure layer.