Abstract: The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area.

Abstract: The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area.

Abstract: A liquid crystal display (LCD) apparatus includes: multiple differential amplifier stages each of which is operable to generate, according to a bias current and an input voltage, an output voltage having a magnitude and a slew rate that correspond respectively to the input voltage and a magnitude of the bias current, and serving as a data voltage of a corresponding pixel unit of an LCD panel; multiple current sources controllable to generate and provide a plurality of the bias currents to the differential amplifier stages, respectively; and a bias voltage generating unit connected electrically to the current sources in a current mirror configuration for generating an input bias current and controlling the current sources to generate the bias currents according to a latch pulse signal. The slew rate of the output voltage corresponds to a logic state of the input bias current.

Abstract: A liquid crystal display apparatus includes a liquid crystal panel and a panel driving device. The panel driving device includes a timing control circuit, a gate driving circuit, and a source driving circuit. The source driving circuit includes a low voltage differential signal (LVDS) receiver, a driving voltage generator, and a controller. The LVDS receiver includes a plurality of receive circuits and a power saving control circuit. Each of the receive circuit performs level conversion upon a data LVDS to generate a logic signal, and operates in a selected one of a normal energy consuming mode and a power saving mode. The power saving control circuit controls the receive circuits to operate in the power saving mode when the power saving control circuit does not receive a power adjustment signal from the controller.

Abstract: An interpolative digital-to-analog (D/A) converter is adapted to convert a N-bit digital signal into an analog signal, where N is a positive integer greater than 1. The interpolative D/A converter includes a router unit that outputs first and second router voltages based on the first and second bits of the digital signal, and an interpolation unit that receives the first and second router voltages from the router unit, and that performs interpolation operation on the first and second router voltages according to the first bit of the digital signal, so as to generate the analog signal having a voltage magnitude ranging from the first router voltage to the second router voltage.

Abstract: An interpolative digital-to-analog (D/A) converter is adapted to convert a N-bit digital signal into an analog signal, where N is a positive integer greater than 1. The interpolative D/A converter includes a router unit that outputs first and second router voltages based on the first and second bits of the digital signal, and an interpolation unit that receives the first and second router voltages from the router unit, and that performs interpolation operation on the first and second router voltages according to the first bit of the digital signal, so as to generate the analog signal having a voltage magnitude ranging from the first router voltage to the second router voltage.

Abstract: A liquid crystal display apparatus includes a liquid crystal panel and a panel driving device. The panel driving device includes a timing control circuit, a gate driving circuit, and a source driving circuit. The source driving circuit includes a low voltage differential signal (LVDS) receiver, a driving voltage generator, and a controller. The LVDS receiver includes a plurality of receive circuits and a power saving control circuit. Each of the receive circuit performs level conversion upon a data LVDS to generate a logic signal, and operates in a selected one of a normal energy consuming mode and a power saving mode. The power saving control circuit controls the receive circuits to operate in the power saving mode when the power saving control circuit does not receive a power adjustment signal from the controller.

Abstract: A dual voltage output circuit includes first and second differential driving units. The first differential driving unit is operable to generate a first output voltage from a pair of first input voltages, has first and second nodes to receive first and second voltage levels, respectively, and has a first intermediate voltage node to receive a first intermediate voltage level. The second differential driving unit is operable to generate a second output voltage from a pair of second input voltages, has third and fourth nodes to receive the first and second voltage levels, respectively, and has a second intermediate voltage node to receive a second intermediate voltage level.

Abstract: A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.

Abstract: A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.

Abstract: A dual voltage output circuit includes first and second differential driving units. The first differential driving unit is operable to generate a first output voltage from a pair of first input voltages, has first and second nodes to receive first and second voltage levels, respectively, and has a first intermediate voltage node to receive a first intermediate voltage level. The second differential driving unit is operable to generate a second output voltage from a pair of second input voltages, has third and fourth nodes to receive the first and second voltage levels, respectively, and has a second intermediate voltage node to receive a second intermediate voltage level.

Abstract: A gate driver structure of TFT-LCD display, comprising: a plurality of first level shifters, each input terminal of which being connected with an input signal; a plurality of output buffers with a plurality of output terminals, each input terminal of the output buffers being connected with each output terminal of the first level shifters; a second level shifter, the input terminal of which being connected with a low voltage signal and the first output terminal of which being connected with a plurality of first level shifters. In addition, the connecting wires between each output terminal of the plurality of first level shifters and each input terminal of the plurality of output buffers are in parallel with a pair of first MOS and second MOS daisy-chained together. The gate of each first MOS is connected with the output terminal of output buffer of the previous cell, and the gate of each second MOS is connected with the second output terminal of the second level shifter.

Abstract: The present invention provides a driving circuit comprising a first data logic unit, a latch unit, and a determining unit. The first data logic unit is utilized for receiving at least a digital data signal and a first control signal, and for selectively inversing the digital data signal to generate a first digital output data signal according to the first control signal. The latch unit is utilized for receiving the first digital output data signal and a second control signal, and for selectively setting a second digital output data signal whether inversed from the first digital output data signal according to the second control signal. The determining unit is utilized for receiving the digital data signal and determining a transition number of the digital data signal in comparison with a previous digital data signal, and outputting the first control signal and the second control signal according to the transition number.

Abstract: A gate driver structure of TFT-LCD display, comprising: a plurality of first level shifters, each input terminal of which being connected with an input signal; a plurality of output buffers with a plurality of output terminals, each input terminal of the output buffers being connected with each output terminal of the first level shifters; a second level shifter, the input terminal of which being connected with a low voltage signal and the first output terminal of which being connected with a plurality of first level shifters. In addition, the connecting wires between each output terminal of the plurality of first level shifters and each input terminal of the plurality of output buffers are in parallel with a pair of first MOS and second MOS daisy-chained together. The gate of each first MOS is connected with the output terminal of output buffer of the previous cell, and the gate of each second MOS is connected with the second output terminal of the second level shifter.