Abstract: A surface mounted package for semiconductor die has a lead frame with a first and elongated die pad which receives three MOSgated die spaced along its length; second, third and fourth die pads laterally spaced from the first die pad and in a row parallel to the first die pad and receiving respective MOSgated die. A central wire bond receiving pad is disposed between the first pad and the spaced second, third and fourth pads. Wire bonds then connect the die into a three phase inverter circuit. Pin connectors extend through a plastic housing covering the top of the lead frame and are connectable, with the die pads, to the surface of a PCB.

Abstract: A dual plane microelectronic relay comprises an input lead frame for carrying an LED an output lead frame carrying a PVG and FETs which are turned on by the output of the PVG in response to its illumination by the LED. Each lead frame is offset in opposite directions so that the lead frame segments carrying the LED and FETs are disposed atop one another while their extending contact pins are coplanar and in line. The PVG and LEDs along the lead frames are accurately located relative to one another by indexed tabs on the side rails of the lead frames. A clear silastic fills the volume between the PVG and LED and the individual units are transfer molded, using an opening in the lead frame rail as a mold gate. A 6 terminal SOP-6 package is formed.