Patents by Inventor Sung-Yen Yeh

Sung-Yen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11355395
    Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
  • Publication number: 20210366774
    Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui KAO, Hui-Zhong ZHUANG, Li-Chung HSU, Sung-Yen YEH, Yung-Chen CHIEN, Jung-Chan YANG, Tzu-Ying LIN
  • Publication number: 20210334447
    Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Inventors: Li-Chung Hsu, Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang-Jui Kao, Chung-Hsing Wang
  • Publication number: 20210232743
    Abstract: A method and system for manufacturing a circuit is disclosed.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Ravi Babu PITTU, Chung-Hsing WANG, Sung-Yen YEH, Li Chung HSU
  • Patent number: 11068637
    Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Chung Hsu, Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang-Jui Kao, Chung-Hsing Wang
  • Patent number: 11003820
    Abstract: A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang
  • Publication number: 20210117603
    Abstract: A method performed by at least one processor includes the following steps. A layout of an integrated circuit (IC) is accessed, wherein the layout has at least one cell. A context group for the cell is determined based on a layout context of the cell, wherein the context group is associated with a timing table. A timing analysis is performed on the layout to determine whether the layout complies with a timing constraint rule according to the timing table. A system including one or more processors including instructions for implementing the method and a non-transitory computer readable storage medium including instructions for implementing the method are also provided.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: ZHE-WEI JIANG, JERRY CHANG JUI KAO, SUNG-YEN YEH, LI CHUNG HSU
  • Patent number: 10977402
    Abstract: A method and system for manufacturing a circuit is disclosed.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh, Li Chung Hsu
  • Publication number: 20200372198
    Abstract: A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: RAVI BABU PITTU, LI-CHUNG HSU, SUNG-YEN YEH, CHUNG-HSING WANG
  • Patent number: 10776545
    Abstract: A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ravi Babu Pittu, Li-Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang
  • Patent number: 10747924
    Abstract: A method for manufacturing an integrated circuit includes determining a static probability pattern of a circuit cell in a timing path of the integrated circuit; determining a timing delay of the circuit cell along the timing path according to the static probability pattern and a pattern based timing database, wherein the pattern based timing database indicates a plurality of reference delays of each timing arc of the circuit cell characterized in response to a plurality of input stress patterns respectively; and manufacturing the integrated circuit according to the timing delay of the circuit cell along the timing path.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ravi Babu Pittu, Li Chung Hsu, Sung-Yen Yeh, Chung-Hsing Wang
  • Publication number: 20200074030
    Abstract: A method and system for manufacturing a circuit is disclosed.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Ravi Babu PITTU, Chung-Hsing Wang, Sung-Yen Yeh, Li Chung Hsu
  • Publication number: 20200019663
    Abstract: A method for manufacturing an integrated circuit includes determining a static probability pattern of a circuit cell in a timing path of the integrated circuit; determining a timing delay of the circuit cell along the timing path according to the static probability pattern and a pattern based timing database, wherein the pattern based timing database indicates a plurality of reference delays of each timing arc of the circuit cell characterized in response to a plurality of input stress patterns respectively; and manufacturing the integrated circuit according to the timing delay of the circuit cell along the timing path.
    Type: Application
    Filed: November 14, 2018
    Publication date: January 16, 2020
    Inventors: RAVI BABU PITTU, LI CHUNG HSU, SUNG-YEN YEH, CHUNG-HSING WANG
  • Patent number: 10503849
    Abstract: A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. A second timing library is generated for a second set of circuit elements for a second set of input parameters. The second timing library is generated by using one or more of the determined device characteristics previously stored in the database. A circuit is formed on a substrate. The circuit includes at least one of the first set of circuit elements or the second set of circuit elements.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ravi Babu Pittu, Chung-Hsing Wang, Sung-Yen Yeh, Li Chung Hsu
  • Publication number: 20190095562
    Abstract: A method includes identifying a timing path in a transistor level from a graph diagram; calculating a plurality of aging costs associated with the timing path based on a plurality of forms of a DC vector; identifying a first form, associated with a first aging cost of the aging costs, from the forms; and identifying a second form, associated with a second aging cost less than the first aging cost, from the forms.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: RAVI BABU PITTU, LI-CHUNG HSU, SUNG-YEN YEH, CHUNG-HSING WANG
  • Patent number: 10176284
    Abstract: A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component; obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Li-Chung Hsu, Tai-Yu Cheng, Sung-Yen Yeh, King-Ho Tam, Yen-Pin Chen, Chung-Hsing Wang
  • Publication number: 20180173832
    Abstract: A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. A second timing library is generated for a second set of circuit elements for a second set of input parameters. The second timing library is generated by using one or more of the determined device characteristics previously stored in the database. A circuit is formed on a substrate. The circuit includes at least one of the first set of circuit elements or the second set of circuit elements.
    Type: Application
    Filed: September 13, 2017
    Publication date: June 21, 2018
    Inventors: Ravi Babu PITTU, Chung-Hsing WANG, Sung-Yen YEH, Li Chung HSU
  • Publication number: 20180096087
    Abstract: A method performed by a processor, the method including preparing a netlist describing a first circuit including an active component, obtaining an original electrical characteristic of the active component, wherein an electrical characteristic of the active component is the original electrical characteristic in a condition that the active component has not been operated; obtaining an aged data describing a variation in the original electrical characteristic, wherein the variation is caused by operating the first circuit under a first mode and a second mode different from the first mode during a time period; providing a simulation result by simulating, based on an aged electrical characteristic, the first circuit operating under the first mode and the second mode during the time period, wherein the aged electrical characteristic is a combination of the original electrical characteristic and the variation.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: LI-CHUNG HSU, TAI-YU CHENG, SUNG-YEN YEH, KING-HO TAM, YEN-PIN CHEN, CHUNG-HSING WANG
  • Patent number: 8826212
    Abstract: A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Yen Yeh, Yeh-Chi Chang, Yen-Pin Chen, Zhe-Wei Jiang, King-Ho Tam, Yuan-Te Hou, Chung-Hsing Wang