Abstract: A memory controller having an improved operating speed controls a memory device in response to a request from a host. The memory controller includes: a processor for driving firmware for controlling communication between the host and the memory device; a map data receiver for receiving map data including a plurality of mapping entries including physical block addresses, for operations to be performed on the memory device from the memory device under the control of the processor; and a map data controller for checking a mapping entry corresponding to the request, which are received from the map data receiver, snooping the detected mapping entry and outputting the detected mapping entry to the processor.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A semiconductor system includes a host device, an operating device, and an interface device. The host device performs a data training operation on the basis of state characteristic information on a data driving circuit provided in the operating device and state characteristic information on a data line.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A controller of a memory system includes a memory, a temperature increment estimating unit and a re-ordering unit. The memory includes a request queue configured to enqueue therein operation requests provided from a host device. The temperature increment estimating unit estimates temperature increments respectively corresponding to the operation requests. The re-ordering unit performs a re-ordering operation for re-arranging the operation requests enqueued in the request queue based on the temperature increments.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory system includes a plurality of memory devices storing data, a processor generating commands at a request of a host, and a flash interface layer transferring the commands to the plurality of memory devices based on power consumptions of the plurality of memory devices, and delaying execution or transfer of commands one or more of the plurality of memory devices when a total peak power of the plurality of memory devices is expected to exceed a limit level.

Abstract: A memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, controls a plurality of memory devices coupled through a plurality of channels. The memory controller includes a request checker for identifying memory devices corresponding to requests received from a host among the plurality of memory devices, and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager for outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator for sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse.

Abstract: Embodiments of the present disclosure relate to a system, a controller, and a method for operating the same. The amount of current that each of multiple power domain modules can use may be determined, and information regarding the amount of usable current may be indicated to each power domain module, thereby controlling the total sum of peak power used by the multiple power domain modules at a specific timepoint to be equal to or lower than a configured value.

Abstract: A memory controller controls a data storage device including a nonvolatile memory in which a recovery code is stored. The memory controller includes: a mode converter for determining an operation mode of the data storage device as a normal mode or a sleep mode, according to power sensing information representing a power consumption of the data storage device, a recovery code storage including a nonvolatile memory, in which a recovery code for a recovery operation is stored, and a code executer for performing the recovery operation by executing the recovery code. The mode converter stores a recovery code address indicating a position of the nonvolatile memory at which the recovery code is stored.

Abstract: A memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, controls a plurality of memory devices coupled through a plurality of channels. The memory controller includes a request checker for identifying memory devices corresponding to requests received from a host among the plurality of memory devices, and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager for outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator for sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A data storage device includes a storage and a controller.

Abstract: Embodiments of the present disclosure relate to a system, a controller, and a method for operating the same. The amount of current that each of multiple power domain modules can use may be determined, and information regarding the amount of usable current may be indicated to each power domain module, thereby controlling the total sum of peak power used by the multiple power domain modules at a specific timepoint to be equal to or lower than a configured value.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, controls a plurality of memory devices coupled through a plurality of channels. The memory controller includes a request checker for identifying memory devices corresponding to requests received from a host among the plurality of memory devices, and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager for outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator for sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse.