Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: The present discloses includes a memory device including a first vertical plug and a second vertical plug that are arranged to be adjacent to each other, a first select line contacting the first vertical plug, a second select line over a same layer as the first select line and contacting the second vertical plug, and an isolation pattern overlapping with a portion of the first vertical plug and a portion of the second vertical plug and separating the first select line from the second select line.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of pages, peripheral circuits programming memory cells included in a selected page of the plurality of pages into a plurality of program states, and a control logic controlling the peripheral circuits to perform a program operation, wherein the control logic controls the peripheral circuits so that a first variable pass voltage applied to a page adjacent to the selected page is different from a pass voltage applied to remaining unselected pages during a program operation for a first set program state having a low threshold voltage distribution, among the plurality of program states.

Abstract: A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: There are provided a semiconductor memory device having improved reliability and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of strings coupled between a bit line and a source line, the plurality of strings including select transistors respectively coupled to select lines and a plurality of memory cells respectively coupled to a plurality of word lines, and a peripheral circuit for performing a read operation on selected memory cells among the plurality of memory cells. The peripheral circuit discharges the select lines earlier than the plurality of word lines in the read operation.