Abstract: An image encoding/decoding method and apparatus for performing representative sample-based intra prediction are provided. An image decoding method may comprise deriving an intra prediction mode of a current block, configuring a reference sample of the current block, and performing intra prediction for the current block based on the intra prediction mode and the reference sample, wherein the intra prediction is representative sample-based prediction.

Abstract: An image encoding/decoding method and apparatus for performing intra prediction using a plurality of reference sample lines are provided. An image decoding method may comprise configuring a plurality of reference sample lines, reconstructing an intra prediction mode of a current block, and performing intra prediction for the current block based on the intra prediction mode and the plurality of reference sample lines.

Abstract: Disclosed herein is a method of decoding an image including determining whether a current block is in a bi-directional optical flow (BIO) mode, calculating gradient information of prediction samples of the current block when the current block is in the BIO mode, and generating a prediction block of the current block using the calculated gradient information, wherein the calculating of the gradient information of the prediction samples of the current block includes calculating the gradient information using at least one neighbor sample adjacent to the prediction samples.

Abstract: The present invention relates to an apparatus and method for encoding and decoding an image by skip encoding. The image-encoding method by skip encoding, which performs intra-prediction, comprises: performing a filtering operation on the signal which is reconstructed prior to an encoding object signal in an encoding object image; using the filtered reconstructed signal to generate a prediction signal for the encoding object signal; setting the generated prediction signal as a reconstruction signal for the encoding object signal; and not encoding the residual signal which can be generated on the basis of the difference between the encoding object signal and the prediction signal, thereby performing skip encoding on the encoding object signal.

Abstract: Disclosed is a method of decoding an image and a method of encoding an image. The method of decoding an image includes: obtaining motion-constrained tile set information; determining, on the basis of the motion-constrained tile set information, a first boundary region of a collocated tile set within a reference picture, which corresponds to a motion-constrained tile set; padding a second boundary region corresponding to the first boundary region; and performing inter prediction on the motion-constrained tile set by using a collocated tile set that includes the padded second boundary region.

Abstract: Provided an electronic device including a main body and a kit connected to the main body, and the main body includes a battery, a first motor, an electric wire connected to the battery, and a first controller connected to the electric wire, the kit includes a second motor supplied with power through the electric wire, an inverter connected to the second motor, and a second controller connected to the electric wire and configured to control driving of the inverter, and the second controller is configured to transmit information to the first controller through switching frequency control of the inverter and control a switching frequency of the inverter so that a current associated with the second motor is greater than zero in a section in which transmission of the information is performed.

Abstract: According to the present invention, an image encoding apparatus comprises: a motion prediction unit which derives motion information on a current block in the form of the motion information including L0 motion information and L1 motion information; a motion compensation unit which performs a motion compensation for the current block on the basis of at least one of the L0 motion information and L1 motion information so as to generate a prediction block corresponding to the current block; and a restoration block generating unit which generates a restoration block corresponding to the current block based on the prediction block. According to the present invention, image encoding efficiency can be improved.

Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.

Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including first select transistors, memory cells, and second select transistors, which are connected between bit lines and a source line; a precharge controller for monitoring a program operation of the memory cells, and changing a precharge mode of unselected strings among strings included in the memory block according to a monitoring result; and a select line voltage generator for generating a positive voltage or a negative voltage, which is applied to a second select line connected to the second select transistors, according to the precharge mode selected in the precharge controller.

Abstract: A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including a plurality of program loops. Each of the plurality of program loops includes a program pulse application operation and a verify operation. The control logic controls the peripheral circuit to store cell status information and apply a program limit voltage. The control logic sets a verify pass reference and applies the program limit voltage determined based on the cell status information.

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a chamber comprising a support, the support configured to have mounted thereon a substrate; at least one channel disposed in the chamber and into which a conductive fluid or a non-conductive fluid is configured to be injected; and a control unit. The control unit includes a first pump and a second pump configured to respectively supply the conductive fluid and the non-conductive fluid to the at least one channel; and a first valve configured to receive the conductive fluid and the non-conductive fluid from the first pump and the second pump, respectively, and control proportions at which the conductive fluid and the non-conductive fluid are injected into the at least one channel.

Abstract: A memory device includes a memory block, peripheral circuit, and control logic. The memory block includes a plurality of pages coupled to a plurality of word lines, respectively. The peripheral circuit is configured to perform a program loop including a program pulse operation of applying a program voltage to a selected word line, and a verify operation of applying at least one verify voltage corresponding to the program voltage to the selected word line and applying a verify pass voltage to unselected word lines. The control logic is configured to increase a level of the verify pass voltage applied to at least one unselected word line among the unselected word lines whenever the peripheral circuit performs the next program loop when threshold voltages of memory cells included in a page coupled to the selected word line are greater than a reference level.

Abstract: A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including a plurality of program loops. Each of the plurality of program loops includes a program pulse application operation and a verify operation. The control logic controls the peripheral circuit to store cell status information and apply a program limit voltage. The control logic sets a verify pass reference and applies the program limit voltage determined based on the cell status information.

Abstract: An RF sensing apparatus configured for use with a plasma processing chamber includes a penetration unit opened in an up/down direction, a main return path unit surrounding all or a portion of the penetration unit, and a secondary return path unit located between the penetration unit and the main return path unit, spaced apart from the main return path unit, and surrounding all or a portion of the penetration unit. The main return path unit and the secondary return path unit include a path through which a current flows in one of the up/down directions.

Abstract: An RF sensing apparatus configured for use with a plasma processing chamber includes a penetration unit opened in an up/down direction, a main return path unit surrounding all or a portion of the penetration unit, and a secondary return path unit located between the penetration unit and the main return path unit, spaced apart from the main return path unit, and surrounding all or a portion of the penetration unit. The main return path unit and the secondary return path unit include a path through which a current flows in one of the up/down directions.

Abstract: Apparatus and method for disturbance rejection in a control system. In some embodiments, a controller is adapted to position a control object. A disturbance observer generates a disturbance compensation value which is applied to reduce position error resulting from application of mechanical disturbance to the control object. The disturbance observer includes an adaptive filter with at least one dead zone providing a pass-through response with a scalar gain of less than one.

Abstract: A memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and a control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation.

Abstract: A plasma processing apparatus includes a chamber including a space for processing a substrate, a substrate stage supporting the substrate within the chamber and including a lower electrode, an upper electrode within the chamber facing the lower electrode, a first power supply including a sinusoidal wave power source configured to apply a sinusoidal wave power to the lower electrode to form plasma within the chamber, and a second power supply configured to apply a nonsinusoidal wave power to the upper electrode to generate an electron beam.

Abstract: Provided herein are a memory device and a method of operating the same. The memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation.

Abstract: A semiconductor memory device may include a memory cell array, a plurality of page buffers respectively connected to a plurality of bit lines of the memory cell array, and a control logic configured to control the plurality of page buffers to perform an operation on the memory cell array, wherein each of the plurality of page buffers senses a current amount, which varies according to a potential level of a corresponding bit line among the plurality of bit lines, at a sensing node to read data, and a precharge potential level at the sensing node is adjusted according to a temperature.