Abstract: A battery pack includes a battery module assembly having at least one battery cell, a pack case configured to accommodate the battery module assembly, and a barrier unit provided on at least one side of the pack case, configured to discharge a vent gas in the pack case to the outside of the pack case and having at least one blocking baffle disposed obliquely to have a predetermined inclination angle.

Abstract: A battery pack includes a plurality of battery modules each including one or more battery cells to store and release energy, each battery module further including an intake portion and an exhaust portion, an intake duct including an intake channel and communicating with the intake portion of each of the plurality of battery modules, and an exhaust duct including an exhaust channel and communicating with the exhaust portion of each of the plurality of battery modules. Each of the plurality of battery modules further includes an opening/closing member configured to close the intake portion when internal pressure increases.

Abstract: A method of mounting a bus-bar frame includes: forming a plurality of cell lead blocks and a battery cell stacked body by alternately stacking a cell lead block and at least one battery cell; disposing a top cover with respective ends on which a bus-bar frame is installed so as to cover the battery cell stacked body; removing the lead blocks from a space between the battery cell stacked body and the bus-bar frame; and installing the bus-bar frame on the battery cell stacked body by rotating the bus-bar frame. The alternately stacking of the cell lead block and the at least one battery cell includes positioning an electrode lead protruding from each battery cell between neighboring ones of the cell lead blocks.

Abstract: A battery pack is configured to improve safety by effectively suppressing heat transfer between battery modules in the present disclosure. A battery pack includes a plurality of battery modules each having one or more battery cells, configured to store and release energy, and stacked in at least one direction; a pack case provided on at least one side of the plurality of battery modules, covering at least a portion of the outside of the plurality of battery modules, and having one or more openings formed therein; and a melting member provided in the opening of the pack case to seal the opening and configured to open the opening by being melted by heat generated from one or more battery modules among the plurality of battery modules.

Abstract: A battery rack includes a plurality of battery modules, each including at least one battery cell, wherein each battery module has at least one venting hole; a rack case accommodating the plurality of battery modules; and a plurality of support brackets disposed in the rack case such that each support bracket supports each battery module and is in communication with the at least one venting hole.

Abstract: Provided is a digital door lock which can issue a master key, can be operated using a terminal having the master key and can be operated using a terminal having a slave key distributed by a user of the terminal having the master key, regardless of whether the digital door lock is connected to a network. The digital door lock includes: a storage unit which stores a master key unique to the digital door lock and recorded at the time of manufacturing the digital door lock; a wireless communication interface which provides a short-range wireless communication function; and a processor which controls the wireless communication interface to transmit the master key to a master control terminal directly connected through the wireless communication interface.

Abstract: A watch including a dial pad, a circular movement disposed adjacent to the dial pad, a circular printed circuit board (PCB) having an inner diameter and an outer diameter, the PCB including a hole defined as the inner diameter and a plurality of integrated circuits (ICs) disposed in a region between the inner diameter and the outer diameter, in which the movement having a diameter smaller than the inner diameter is shaped and sized to fit into the hole, a first battery disposed adjacent to the PCB and supplies a first operating voltage only to the PCB, and a case dimensioned and shaped to receive the dial pad, the movement, the PCB, and the first battery.

Abstract: A watch including a dial pad, a circular movement disposed adjacent to the dial pad, a circular printed circuit board (PCB) having an inner diameter and an outer diameter, the PCB including a hole defined as the inner diameter and a plurality of integrated circuits (ICs) disposed in a region between the inner diameter and the outer diameter, in which the movement having a diameter smaller than the inner diameter is shaped and sized to fit into the hole, a first battery disposed adjacent to the PCB and supplies a first operating voltage only to the PCB, and a case dimensioned and shaped to receive the dial pad, the movement, the PCB, and the first battery.

Abstract: Methods of managing data of a storage device responsive to temperature can include measuring a temperature of the storage device, changing a duration of a refresh interval of the buffer memory responsive to the measured temperatures, changing a number of refresh bursts during the refresh interval responsive to the measured temperature, and refreshing data of the buffer memory based on the refresh interval and the number of the refresh bursts that are changed responsive to temperature.

Abstract: Methods of managing data of a storage device responsive to temperature can include measuring a temperature of the storage device, changing a duration of a refresh interval of the buffer memory responsive to the measured temperatures, changing a number of refresh bursts during the refresh interval responsive to the measured temperature, and refreshing data of the buffer memory based on the refresh interval and the number of the refresh bursts that are changed responsive to temperature.

Abstract: A test device is provided. The test device includes a first via which transmits a supply voltage, a second via which transmits a ground voltage, a test board including a plurality of test signal vias for transmitting a plurality of test signals, a capacitor disposed on an upper part of the test board and connected between the first via and the second via, and a test socket which electrically connects a device under test (DUT) with the test board. The test socket includes a first region including a flat lower surface bordering the test board, a second region including an uneven lower surface, a plurality of first contactors which are disposed in the first region and which are connected to the plurality of vias, and two second contactors which are disposed in the second region and which are connected to two terminals of the capacitor.

Abstract: A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal.

Abstract: The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal durin

Abstract: A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input port that is configured to receive a control signal that identifies a type of signal that is input to the first input port. Related methods of testing semiconductor memory devices are also provided.

Abstract: The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal durin

Abstract: A memory device and a method of controlling an input signal of the memory device. In the method of controlling an input signal according to test modes, it is determined whether the input signal is in a first test mode or a second test mode. If the memory device is in the first test mode, in response to a control signal, an input signal is received through input pins. In response to a mode signal, the input signal is separated into data and an address. The separated data and address is applied to the core of a memory device. If the memory device is in the second test mode, an input signal is received through input pins and inverting input pins. In response to a mode signal, an address is separated from the input signal received through the input pins and the data is separated from the input signal received through the inverting input pins. The separated data and address are applied to the core of a memory device.

Abstract: There are provided an apparatus and method for testing semiconductor memory devices, in which the frequencies of test pattern signals can be selectively changed. The test apparatus includes a main tester, an input frequency converter, and an output frequency converter. The main tester generates first input test signals with a first frequency, a first program control signal, and a second program control signal, receives first output test pattern signals with the first frequency, and determines an operating performance of a semiconductor memory device. The input frequency converter converts the first input test pattern signals into second input test pattern signals with a second frequency in response to the first program control signal, and applies the second input test pattern signals to the semiconductor memory device.

Abstract: A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal.

Abstract: A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Abstract: A method of providing supplemental service for conference calling using an intelligent peripheral in an intelligent network is disclosed. By using a specific resource of an IP, various good quality services can be provided by connecting a Service Switching Point (SSP), a Service control Point (SCP), and an Intelligent Peripheral (IP) by a No. 7 common channel signaling network.