Abstract: The present disclosure relates to a cathode active material for an all-solid-state battery with a controlled particle size and a method for preparing the same. In particular, the cathode active material includes lithium and a transition metal, wherein the cathode active material has a single peak in the range of 1 ?m to 10 ?m as a result of particle size distribution (PSD) analysis.

Abstract: Provided is a method and apparatus for receiving a reference signal. A wireless user device may determine, based on a synchronization signal (SS) block index and based on an index associated with a time interval, an initialization value associated with a reference signal for a physical broadcast channel (PBCH). The wireless user device may receive, based on the initialization value and based on a frequency domain shift value, the reference signal via at least one resource element (RE). The reference signal may be mapped, based on the frequency domain shift value, to the at least one RE. The wireless user device may receive the PBCH.

Abstract: In various embodiments, an antenna array may comprise a dielectric; a first patch antenna disposed on a first region of the dielectric; a second patch antenna disposed on a second region of the dielectric; and a ground layer including a first sub-ground layer in contact with a lower portion of the first region of the dielectric, a third sub-ground layer in contact with a lower portion of the second region of the dielectric, and a second sub-ground layer spaced apart from a lower portion between the first region and the second region of the dielectric.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A negative voltage switching device includes a first switching circuit configured to transmit a first negative voltage, a second switching circuit configured to transmit a second negative voltage, and a switching selection circuit configured to select one of the first switching circuit or the second switching circuit for transmitting one of the first negative voltage and the second negative voltage to an output terminal.

Abstract: The present invention relates to generating training data for performing artificial intelligence. A method and apparatus for generating section data of a visual work instruction for performing artificial intelligence are provided for generating data for searching a user's desired section in a visual work instruction using an artificial intelligence-based text search model.

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: Various embodiments of the present disclosure relate to a non-volatile memory device including a sense amplifier and an operation method thereof. The non-volatile memory device may include: a memory cell array comprising a plurality of memory cells; and the sense amplifier configured to read data of the plurality of memory cells and output the read data. The sense amplifier may include: a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification.

Abstract: A method of a charging apparatus for controlling wireless charging is provided. The method includes detecting an electronic device, determining a charging method corresponding to the detected electronic device, and wirelessly charging the electronic device by selecting a coil corresponding to the determined charging method.

Abstract: In various embodiments, an antenna array may comprise a dielectric; a first patch antenna disposed on a first region of the dielectric; a second patch antenna disposed on a second region of the dielectric; and a ground layer including a first sub-ground layer in contact with a lower portion of the first region of the dielectric, a third sub-ground layer in contact with a lower portion of the second region of the dielectric, and a second sub-ground layer spaced apart from a lower portion between the first region and the second region of the dielectric.

Abstract: A wireless power transmission apparatus according to various embodiments may comprise a plurality of patch antennas, a communication circuit, and a processor. The processor may be configured to perform a control to form an RF wave of a first beam width via the plurality of patch antennas, receive, from an electronic apparatus, via the communication circuit, sensing data for at least one of a movement of the electronic apparatus or an orientation of the electronic apparatus, and adjust a beam width of the RF wave formed by the plurality of patch antennas from the first beam width to a second beam width at least on the basis of the received sensing data.

Abstract: A non-volatile memory device includes a first fuse cell array and a second fuse cell array, spaced from each other; a first ground ring region and a second ground ring region disposed to surround the first fuse cell array and the second fuse cell array, respectively; a third ground ring region configured to connect the first ground ring region and the second ground ring region; a power ring region disposed to surround the first ground ring region and the second ground ring region; and an address decoder, disposed between the first fuse cell array and the second fuse cell array, configured to supply a word line signal to each of the first fuse cell array and the second fuse cell array. The ground ring regions supply a ground voltage to each of the first fuse cell array and the second fuse cell array.

Abstract: An octo mode program and erase operation method to reduce test time in a non-volatile memory device. M/8 word lines corresponding to an octo row, among M word lines, are simultaneously selected, and a write voltage is applied to memory cells connected to M/8 word lines corresponding to the octo row. A voltage that is different from the write voltage is applied to memory cells connected to the rest of word lines, except for M/8 word lines corresponding to the octo row, when the octo signal is applied to an address decoder.

Abstract: A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.

Abstract: A negative voltage switching device includes a first switching circuit configured to transmit a first negative voltage, a second switching circuit configured to transmit a second negative voltage, and a switching selection circuit configured to select one of the first switching circuit or the second switching circuit for transmitting one of the first negative voltage and the second negative voltage to an output terminal

Abstract: An eFuse cell is provided. The eFuse cell may include a first PMOS transistor and a first NMOS transistor configured to receive a programmed state selection (BLOWB) signal, a second PMOS transistor and a second NMOS transistor configured to receive a write word line bar (WWLB) for a program operation, a first read NMOS transistor and a second read NMOS transistor configured to receive a read word line (RWL) for a read operation, a program transistor configured to control a program current to flow for a fusing operation, and an eFuse connected between the first read NMOS transistor and the second read NMOS transistor.

Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.

Abstract: A search method using an artificial intelligence based information retrieval model and a method for training the artificial intelligence based information retrieval model used for the method are provided. In the method, even if there is no labeled data and only a corpus exists, the artificial intelligence based information retrieval model can be trained using the weak-supervision methodology. Search can be performed by dividing documents into passages having short lengths. Compared to an information retrieval model based on unsupervised learning, improved search results are provided.