Patents by Inventor Sung-Chieh Lin
Sung-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176093Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 9990985Abstract: A memory device includes a memory array that comprises at least a bit cell configured to store a data bit; a tracking circuit, coupled to the memory array, and configured to provide an enable signal in response to a first timing edge of a clock signal, wherein the enable signal emulates an electrical signal path propagating the memory array; and a control logic circuit comprising a timing control engine coupled to the tracking circuit, wherein the timing control engine is configured to select a faster timing edge between a second timing edge of the clock signal and a third timing edge of the enable signal so as to terminate an ongoing operation of the bit cell.Type: GrantFiled: February 9, 2017Date of Patent: June 5, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuoyuan Hsu, Sung-Chieh Lin
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Publication number: 20180151219Abstract: A memory device includes a memory array that comprises at least a bit cell configured to store a data bit; a tracking circuit, coupled to the memory array, and configured to provide an enable signal in response to a first timing edge of a clock signal, wherein the enable signal emulates an electrical signal path propagating the memory array; and a control logic circuit comprising a timing control engine coupled to the tracking circuit, wherein the timing control engine is configured to select a faster timing edge between a second timing edge of the clock signal and a third timing edge of the enable signal so as to terminate an ongoing operation of the bit cell.Type: ApplicationFiled: February 9, 2017Publication date: May 31, 2018Inventors: Kuoyuan Hsu, Sung-Chieh Lin
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Patent number: 9966378Abstract: A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.Type: GrantFiled: September 12, 2016Date of Patent: May 8, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: David Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Patent number: 9558841Abstract: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.Type: GrantFiled: June 14, 2013Date of Patent: January 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Chieh Lin, Kuo-Yuan Hsu, Wei-Li Liao, Chen-Ming Hung, Yun-Han Chen, Shao-Cheng Wang
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Publication number: 20160379983Abstract: A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.Type: ApplicationFiled: September 12, 2016Publication date: December 29, 2016Inventors: David YEN, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Patent number: 9449888Abstract: A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.Type: GrantFiled: January 12, 2015Date of Patent: September 20, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: David Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Patent number: 9412438Abstract: A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.Type: GrantFiled: January 24, 2014Date of Patent: August 9, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai Fan, Kuoyuan (Peter) Hsu, Bing Wang, Sung-Chieh Lin
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Patent number: 9177668Abstract: A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.Type: GrantFiled: June 11, 2013Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sung-Chieh Lin, Jiann-Tseng Huang, Wei-Li Liao, Kuoyuan Hsu
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Patent number: 9135099Abstract: A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.Type: GrantFiled: March 29, 2012Date of Patent: September 15, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Han Chen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Patent number: 9117506Abstract: In a method, a current value of a memory cell of a tracked circuit is determined. The memory cell is coupled with a data line. A tracking current value of a tracking memory cell of a tracking circuit is determined. The tracking memory cell is coupled with a tracking data line. A current value of a transistor of the tracking circuit is determined, based on a current value of a transistor of the tracked circuit, the current value of the memory cell, and the tracking current value of the tracking memory cell. A signal of the tracked circuit is generated based on a signal of the tracking circuit.Type: GrantFiled: December 31, 2013Date of Patent: August 25, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan (Peter) Hsu, Sung-Chieh Lin
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Publication number: 20150213880Abstract: A circuit comprises a first transistor, a capacitive component, a second transistor, and a data line. The first transistor has a threshold voltage value. A first terminal of the first transistor is coupled with a first terminal of the capacitive component and a second terminal of the second transistor. A second terminal of the first transistor is configured to receive a second-terminal voltage value. A third terminal of the first transistor is configured to receive a third-terminal voltage value. A first terminal of the second transistor is coupled with the data line. A third terminal of the second transistor is configured to receive a second-transistor control signal. The first transistor is configured to be on and off to maintain the data line at a data line voltage value.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai FAN, Kuoyuan (Peter) HSU, Bing WANG, Sung-Chieh LIN
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Publication number: 20150187397Abstract: In a method, a current value of a memory cell of a tracked circuit is determined. The memory cell is coupled with a data line. A tracking current value of a tracking memory cell of a tracking circuit is determined. The tracking memory cell is coupled with a tracking data line. A current value of a transistor of the tracking circuit is determined, based on a current value of a transistor of the tracked circuit, the current value of the memory cell, and the tracking current value of the tracking memory cell. A signal of the tracked circuit is generated based on a signal of the tracking circuit.Type: ApplicationFiled: December 31, 2013Publication date: July 2, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan (Peter) HSU, Sung-Chieh LIN
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Publication number: 20150140748Abstract: A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.Type: ApplicationFiled: January 12, 2015Publication date: May 21, 2015Inventors: David YEN, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Patent number: 8946825Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.Type: GrantFiled: March 28, 2012Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: David Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Publication number: 20140369105Abstract: A circuit includes a fuse cell, a sense circuit and an output control circuit. The fuse cell includes an electrical fuse. The sense circuit is electrically coupled to the fuse cell and configured for generating a sense signal indicative of a programmed condition of the electrical fuse, at an output of the sense circuit. The output control circuit is electrically coupled to the output of the sense circuit, and the output control circuit is configured for latching the sense signal indicative of the electrical fuse having been programmed, during a read operation of the fuse cell.Type: ApplicationFiled: June 14, 2013Publication date: December 18, 2014Inventors: Sung-Chieh LIN, Kuo-Yuan HSU, Wei-Li LIAO, Chen-Ming HUNG, Yun-Han CHEN, Shao-Cheng WANG
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Patent number: 8847350Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.Type: GrantFiled: August 30, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Wei-Li Liao, Yun-Han Chen, Chen-Ming Hung
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Patent number: 8824234Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.Type: GrantFiled: February 20, 2013Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, David Yen, Wei-Li Liao, Jiann-Tseng Huang, Kuoyuan (Peter) Hsu
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Patent number: 8787109Abstract: A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse.Type: GrantFiled: May 8, 2012Date of Patent: July 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Li Liao, Sung-Chieh Lin, Kuoyuan (Peter) Hsu