Abstract: A Compute Express Link (CXL) device, including: a CXL.io module configured to set a prefetch management capability based on a CXL.io request received from a host device; a memory controller configured to access a memory device; and a CXL.mem module configured to: receive a prefetch indicator from the CXL.io module, and prefetch first data corresponding to the at least one prefetch indicator using the memory controller, and store the prefetched first data, wherein the prefetch indicator includes address information about a prefetch region in which the first data is stored, and prefetch control/status information, and wherein the CXL.mem module is further configured to output the first data stored in the CXL.mem module to the host device based on receiving a data access request from the host device and determining that an address of requested data associated with the data access request belongs to the prefetch region.

Abstract: A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.

Abstract: A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

Abstract: A serial communication interface circuit includes a transmitter configured to convert first parallel data into first serial data and transmit the first serial data through an output port; a receiver configured to receive second serial data through an input port and convert the second serial data into second parallel data; a test controller configured to generate at least one test control signal; and an embedded external loopback circuit configured to form an external loopback path between the output port and the input port to receive the first serial data and output the second serial data according to at least one channel model in response to the at least one test control signal in a test mode.

Abstract: A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

Abstract: A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.

Abstract: A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.

Abstract: A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.

Abstract: A serial communication method for a layered communication architecture includes a first layer, a second layer that is higher than the first layer, and a third layer that is higher than the second layer. The serial communication method includes transferring a first signal to the second layer based on a signal received through a communication line, the transferring performed by the first layer. The serial communication method further includes informing the third layer of reception of the first signal, the informing performed by the second layer; responding to the second layer based on whether there is a task to be performed, the responding performed by the third layer; transferring a second signal to the first layer based on a response from the third layer the transferring performed by the second layer; and entering a power saving state according to the second signal, the entering performed by the first layer.

Abstract: A serial communication interface circuit includes a transmitter configured to convert first parallel data into first serial data and transmit the first serial data through an output port; a receiver configured to receive second serial data through an input port and convert the second serial data into second parallel data; a test controller configured to generate at least one test control signal; and an embedded external loopback circuit configured to form an external loopback path between the output port and the input port to receive the first serial data and output the second serial data according to at least one channel model in response to the at least one test control signal in a test mode.

Abstract: A transmitting circuit includes a serializer that converts parallel data into serial data based on a clock signal, a driver that generates differential signals based on the serial data, and a clock buffer that provides the clock signal to the serializer. In a standby state, the clock buffer cuts off the clock signal and the serializer outputs the serial data according to a reset signal such that standby differential signals indicating the standby state are generated by the driver irrespective of the clock signal.

Abstract: A transmitting circuit includes a serializer that converts parallel data into serial data based on a clock signal, a driver that generates differential signals based on the serial data, and a clock buffer that provides the clock signal to the serializer. In a standby state, the clock buffer cuts off the clock signal and the serializer outputs the serial data according to a reset signal such that standby differential signals indicating the standby state are generated by the driver irrespective of the clock signal.

Abstract: A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals.

Abstract: A transmitting circuit includes a plurality of transmitters, an operation clock generator, and a clock divider. Each of the transmitters outputs data serially. The operation clock generator generates an operation clock signal. The clock divider divides the operation clock signal to generate a symbol clock signal. The plurality of transmitters receives the operation clock signal and the symbol clock signal in common. A clock signal provided to one transmitter is equally synchronized with a clock signal provided to other transmitter(s).

Abstract: A transmitting circuit includes a plurality of transmitters, an operation clock generator, and a clock divider. Each of the transmitters outputs data serially. The operation clock generator generates an operation clock signal. The clock divider divides the operation clock signal to generate a symbol clock signal. The plurality of transmitters receives the operation clock signal and the symbol clock signal in common. A clock signal provided to one transmitter is equally synchronized with a clock signal provided to other transmitter(s).

Abstract: A receiving circuit includes a termination resistance circuit and a resistance adjustment circuit. The termination resistance circuit is configured to receive a first differential signal via a first input terminal and a second differential signal via a second input terminal, and to be selectively connected to the first and second input terminals. The termination resistance circuit has an adjustable resistance value. The resistance adjustment circuit is configured to decrease the resistance value of the termination resistance circuit in response to a signal reception preparation command and connection of the termination resistance circuit to the first and second input terminals.

Abstract: A serial communication method for a layered communication architecture includes a first layer, a second layer that is higher than the first layer, and a third layer that is higher than the second layer. The serial communication method includes transferring a first signal to the second layer based on a signal received through a communication line, the transferring performed by the first layer. The serial communication method further includes informing the third layer of reception of the first signal, the informing performed by the second layer; responding to the second layer based on whether there is a task to be performed, the responding performed by the third layer; transferring a second signal to the first layer based on a response from the third layer the transferring performed by the second layer; and entering a power saving state according to the second signal, the entering performed by the first layer.

Abstract: A power supply module and a power supply method corresponding to an electronic device. The power supply module includes a low-dropout (LDO) voltage regulator to adjust an input signal received from a battery and output a stabilized output signal, and an external load calculation circuit to calculate an external load value at a power output node of the LDO voltage regulator and stabilize the output signal based on the external load value.

Abstract: Provided are a scanning probe microscope and a method of operating the same. The scanning probe microscope includes a chuck configured to fix an object. A stacker is configured to load one or more cantilevers onto a head module. A stacker lifting element is configured to move the stacker in an up and down direction.

Abstract: Provided are a scanning probe microscope and a method of operating the same. The scanning probe microscope includes a chuck configured to fix an object. A stacker is configured to load one or more cantilevers onto a head module. A stacker lifting element is configured to move the stacker in an up and down direction.