Patents by Inventor Sung-Hae Lee
Sung-Hae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932618Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.Type: GrantFiled: March 13, 2023Date of Patent: March 19, 2024Assignee: ILDONG PHARMACEUTICAL CO., LTD.Inventors: Hong Chul Yoon, Kyung Mi An, Myong Jae Lee, Jin Hee Lee, Jeong-geun Kim, A-rang Im, Woo Jin Jeon, Jin Ah Jeong, Jaeho Heo, Changhee Hong, Kyeojin Kim, Jung-Eun Park, Te-ik Sohn, Changmok Oh, Da Hae Hong, Sung Wook Kwon, Jung Ho Kim, Jae Eui Shin, Yeongran Yoo, Min Whan Chang, Eun Hye Jang, In-gyu Je, Ji Hye Choi, Gunhee Kim, Yearin Jun
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Patent number: 11923610Abstract: In various embodiments, an antenna array may comprise a dielectric; a first patch antenna disposed on a first region of the dielectric; a second patch antenna disposed on a second region of the dielectric; and a ground layer including a first sub-ground layer in contact with a lower portion of the first region of the dielectric, a third sub-ground layer in contact with a lower portion of the second region of the dielectric, and a second sub-ground layer spaced apart from a lower portion between the first region and the second region of the dielectric.Type: GrantFiled: May 24, 2017Date of Patent: March 5, 2024Assignees: Samsung Electronics Co., Ltd., HONGIK UNIVERSITY INDUSTRY-ACADEMIA COOPERATION FOUNDATIONInventors: Jae-Hyun Park, Jeong-Hae Lee, Min-Seo Park, Young-Ho Ryu, Sung-Bum Park, Kwi-Seob Um, Chong-Min Lee, Chang-Hyun Lee
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Publication number: 20230204897Abstract: A lens module includes a lens barrel in which a plurality of lenses are disposed, and a lens holder to which the lens barrel is coupled, wherein the lens holder includes a fastening portion fastening the lens barrel, the lens barrel includes a fastening blade coupled to the fastening portion of the lens holder, and the fastening portion includes a stepped portion preventing rotation in a direction, opposite to a direction in which the fastening blade rotates for fastening.Type: ApplicationFiled: April 8, 2022Publication date: June 29, 2023Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sung Ho KANG, Jae Man PARK, Jae Kyung KIM, Sung Hoon KIM, Sung Hae LEE, Sung Taek OH
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Patent number: 10453707Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.Type: GrantFiled: October 24, 2017Date of Patent: October 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Seok Cho, Hyung Joon Kim, Jung Ho Kim, Joong Yun Ra, Bi O Kim, Jae Young Ahn, Ki Yong Oh, Sung Hae Lee
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Patent number: 10276589Abstract: A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.Type: GrantFiled: April 27, 2017Date of Patent: April 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung Joon Kim, Yong Seok Cho, BiO Kim, Jung Ho Kim, Joong Yun Ra, Sung Hae Lee
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Publication number: 20180315621Abstract: A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.Type: ApplicationFiled: October 24, 2017Publication date: November 1, 2018Inventors: Yong Seok CHO, Hyung Joon KIM, Jung Ho KIM, Joong Yun RA, Bi O KIM, Jae Young AHN, Ki Yong OH, Sung Hae LEE
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Publication number: 20180122821Abstract: A method of manufacturing a semiconductor device includes forming a mold structure including alternately stacked mold insulating and sacrificial layers on a substrate, forming a vertical structure through the mold structure, forming side openings by removing the sacrificial, forming a preliminary dielectric layer in the side openings, forming a dielectric layer by heat-treating the preliminary dielectric layer, removing a surface layer of the dielectric layer, forming a first conductive layer covering the dielectric layer in the side openings, and forming a second conductive layer covering the first conductive layer and filling the side openings.Type: ApplicationFiled: April 27, 2017Publication date: May 3, 2018Inventors: Hyung Joon KIM, Yong Seok CHO, BiO KIM, Jung Ho KIM, Joong Yun RA, Sung Hae LEE
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Patent number: 9613800Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.Type: GrantFiled: February 18, 2015Date of Patent: April 4, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Yong Go, Jin-Gyun Kim, Dong-Kyum Kim, Jung-Ho Kim, Koong-Hyun Nam, Sung-Hae Lee, Eun-Young Lee, Jung-Geun Jee, Eun-Yeoung Choi, Ki-Hyun Hwang
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Publication number: 20150235836Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.Type: ApplicationFiled: February 18, 2015Publication date: August 20, 2015Inventors: Hyun-Yong GO, Jin-Gyun KIM, Dong-Kyum KIM, Jung-Ho KIM, Koong-Hyun NAM, Sung-Hae LEE, Eun-Young LEE, Jung-Geun JEE, Eun-Yeoung CHOI, Ki-Hyun HWANG
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Patent number: 8927366Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.Type: GrantFiled: September 11, 2012Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-hae Lee, Ki-hyun Hwang, Jin-gyun Kim
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Patent number: 8710564Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.Type: GrantFiled: March 13, 2012Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
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Publication number: 20140054675Abstract: According to example embodiments, a vertical type semiconductor device includes a pillar structure on a substrate. The pillar structure includes a semiconductor pattern and a channel pattern. The semiconductor pattern includes an impurity region. A first word line structure faces the channel pattern and is horizontally extended while surrounding the pillar structure. A second word line structure has one side facing the impurity region of the semiconductor pattern and another side facing the substrate. A common source line is provided at a substrate portion adjacent to a sidewall end portion of the second word line structure.Type: ApplicationFiled: July 18, 2013Publication date: February 27, 2014Inventors: Chae-Ho Kim, Sung-Hae Lee, Toshiro Nakanishi, Dong-Woo Kim
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Patent number: 8497555Abstract: A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.Type: GrantFiled: November 17, 2011Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Gyun Kim, Ki-Hyun Hwang, Sung-Hae Lee, Ji-Hoon Choi
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Publication number: 20130089974Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.Type: ApplicationFiled: September 11, 2012Publication date: April 11, 2013Inventors: Sung-hae Lee, Ki-hyun Hwang, Jin-gyun Kim
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Publication number: 20130020346Abstract: An apparatus for storing, heating, and dispensing cleansing tissue. An enclosed housing includes a bottom floor provided with upwardly extending peripheral walls having inner sidewalls and upper edges. The housing includes a top cover having a closed position in sealing relation with the peripheral walls and an open position providing selective access to the enclosed volume of said housing. A heating plate, adapted to move freely upwardly and downwardly within the enclosed volume of the housing is also provided. The heating plate includes at least one heating element, and has an aperture passing therethrough from an upper side to a lower side. An electrical power source is provided, having an output interconnected to the heating element. A stack of cleansing tissue is provided in the housing, located between the lower side of the heating plate and the bottom floor. Individual tissues are removable through the aperture in the heating plate.Type: ApplicationFiled: July 17, 2012Publication date: January 24, 2013Inventor: SUNG HAE LEE
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Patent number: 8264026Abstract: Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.Type: GrantFiled: January 27, 2010Date of Patent: September 11, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hae Lee, Byong-Sun Ju, Suk-Jin Chung, Young-Sun Kim
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Publication number: 20120168904Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.Type: ApplicationFiled: March 13, 2012Publication date: July 5, 2012Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
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Publication number: 20120153291Abstract: A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.Type: ApplicationFiled: November 17, 2011Publication date: June 21, 2012Inventors: Jin-Gyun KIM, Ki-Hyun HWANG, Sung-Hae LEE, Ji-Hoon CHOI
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Patent number: 8159012Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.Type: GrantFiled: September 26, 2008Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
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Publication number: 20110179569Abstract: A bed rail including first and second legs for attachment to a bed or crib. The legs fit between the mattress and the mattress support frame extending transversely from one side of the crib to the other. The proximate end of each leg is pivotally attached to a respective lower corner of an elongated side panel. Raised, the side panel extends vertically above the mattress to provide a safety restraint on one side of the crib. Unlocked, the panel may be swung into a lowered position. Means is also provided for securing the distal end of the legs to the mattress support frame at a location on the other side of the crib. Also disclosed is a safety bolster for use with the bed rail including an upper head portion extending above the mattress and a lower foot portion extending between the mattress and said side panel.Type: ApplicationFiled: January 16, 2011Publication date: July 28, 2011Inventors: Thomas M. Hayano, Sung Hae Lee, Bruce P. McKendry