Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.

Abstract: An example display device includes a display element having at least one portion which can be changed into a curved shape; and a flexible window member stacked onto the display element, wherein the thickness of a portion of the window member is less than that of the other portions.

Abstract: A storage device having improved performance includes: a plurality of memory devices, each memory device including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to be in communication with the plurality of memory devices to provide a read command for instructing a read operation on the plurality of memory blocks to read out data and provide a read enable signal to the memory devices during at least part of an idle time of the channel, which occurs while the read operation is being performed. The plurality of memory devices output first data to the memory controller through the channel in response to the read enable signal, wherein the first data is different from the data previously read out by the read operation that provides the read enable signal in response to the read command.

Abstract: A memory system includes a memory device and a memory controller. The memory controller transmits a data read command to the memory device, inputs N read enable toggle signals to the memory device in order for the memory device to output the data requested by the data read command requests, and inputs an additional read enable toggle signal to the memory device. The memory device outputs status information of the memory device to the memory controller in response to the additional read enable toggle signal.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on selected memory cells, among the plurality of memory cells. The control logic controls the read operation of the peripheral circuit in response to a read command that is received from an external device and determines whether to perform a discharge operation of word lines that are connected to the plurality of memory cells based on a type of the read command.

Abstract: An example display device includes a display element having at least one portion which can be changed into a curved shape; and a flexible window member stacked onto the display element, wherein the thickness of a portion of the window member is less than that of the other portions.

Abstract: Provided herein is a memory device and a storage device including the same. The memory device includes an input/output circuit configured to receive a command, an address, and data from a memory controller. The memory device also includes control logic configured to control a peripheral circuit of the memory device so that an operation of storing the data in a memory cell of the memory device is performed based on the command and the address received from the input/output circuit. The input/output circuit includes a queue layer configured to temporarily store the command and the address and to output the command and the address to the control logic based on at least one of a rising edge and a falling edge of a write enable signal received by the memory device from the memory controller.

Abstract: An example display device includes a display element having at least one portion which can be changed into a curved shape; and a flexible window member stacked onto the display element, wherein the thickness of a portion of the window member is less than that of the other portions.

Abstract: A storage device having improved performance includes: a plurality of memory devices, each memory device including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to be in communication with the plurality of memory devices to provide a read command for instructing a read operation on the plurality of memory blocks to read out data and provide a read enable signal to the memory devices during at least part of an idle time of the channel, which occurs while the read operation is being performed. The plurality of memory devices output first data to the memory controller through the channel in response to the read enable signal, wherein the first data is different from the data previously read out by the read operation that provides the read enable signal in response to the read command.

Abstract: A memory system includes a memory device and a memory controller. The memory controller transmits a data read command to the memory device, inputs N read enable toggle signals to the memory device in order for the memory device to output the data requested by the data read command requests, and inputs an additional read enable toggle signal to the memory device. The memory device outputs status information of the memory device to the memory controller in response to the additional read enable toggle signal.

Abstract: Provided herein is a memory device and a storage device including the same. The memory device includes an input/output circuit configured to receive a command, an address, and data from a memory controller. The memory device also includes control logic configured to control a peripheral circuit of the memory device so that an operation of storing the data in a memory cell of the memory device is performed based on the command and the address received from the input/output circuit. The input/output circuit includes a queue layer configured to temporarily store the command and the address and to output the command and the address to the control logic based on at least one of a rising edge and a falling edge of a write enable signal received by the memory device from the memory controller.

Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.

Abstract: Provided herein is a semiconductor memory device including a memory cell array, a peripheral circuit, an operation information storage, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a read operation for setup information stored in the memory cell array. The operation information storage may store the setup information. The control logic may control a read operation of the peripheral circuit and a storage operation of the operation information storage. The control logic may control the peripheral circuit and the operation information storage such that a storage section in which the operation information storage stores first setup information and a read section in which the peripheral circuit reads second setup information from the memory cell array are at least partially overlapped with each other.

Abstract: An example display device includes a display element having at least one portion which can be changed into a curved shape; and a flexible window member stacked onto the display element, wherein the thickness of a portion of the window member is less than that of the other portions.

Abstract: An example display device includes a display element having at least one portion which can be changed into a curved shape; and a flexible window member stacked onto the display element, wherein the thickness of a portion of the window member is less than that of the other portions.

Abstract: Disclosed in various examples of the present invention are a display device and an electronic device having the same, the display device comprising: a display element; and a guide unit arranged on the display element, wherein the guide unit guides a propagation pathway of the light emitted from the display element. The display device and the electronic device having the same can provide a comfortable viewing environment by using the guide unit so as to guide the propagation pathway of the light emitted from the display element. The display device and the electronic device having the same can be variously implemented according to the examples.

Abstract: Provided herein is a semiconductor memory device including a memory cell array, a peripheral circuit, an operation information storage, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a read operation for setup information stored in the memory cell array. The operation information storage may store the setup information. The control logic may control a read operation of the peripheral circuit and a storage operation of the operation information storage. The control logic may control the peripheral circuit and the operation information storage such that a storage section in which the operation information storage stores first setup information and a read section in which the peripheral circuit reads second setup information from the memory cell array are at least partially overlapped with each other.

Abstract: An example display device includes a display element having at least one portion which can be changed into a curved shape; and a flexible window member stacked onto the display element, wherein the thickness of a portion of the window member is less than that of the other portions.

Abstract: Disclosed in various embodiments of the present invention are a display device and an electronic device having same, the display device comprising: a display element having at least one portion which can be changed into a curved shape; and a flexible window member stacked onto the display element, wherein the thickness of a portion of the window member is less than that of the other portions. The display device and the electronic device having same may vary according to embodiments.

Abstract: An electronic device is provided. The electronic device may include a display module, a bracket disposed on a rear surface of the display module, and a first adhesive member which fixes at least a portion of the display module to the bracket, between the display module and the bracket. The first adhesive member may have adhesive force which is reduced to a specified value or less by at least one of force, light, and/or heat applied from outside.