Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on selected memory cells, among the plurality of memory cells. The control logic controls the read operation of the peripheral circuit in response to a read command that is received from an external device and determines whether to perform a discharge operation of word lines that are connected to the plurality of memory cells based on a type of the read command.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on selected memory cells, among the plurality of memory cells. The control logic controls the read operation of the peripheral circuit in response to a read command that is received from an external device and determines whether to perform a discharge operation of word lines that are connected to the plurality of memory cells based on a type of the read command.

Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.

Abstract: A memory system includes a memory device and a memory controller. The memory controller transmits a data read command to the memory device, inputs N read enable toggle signals to the memory device in order for the memory device to output the data requested by the data read command requests, and inputs an additional read enable toggle signal to the memory device. The memory device outputs status information of the memory device to the memory controller in response to the additional read enable toggle signal.

Abstract: A storage device having improved performance includes: a plurality of memory devices, each memory device including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to be in communication with the plurality of memory devices to provide a read command for instructing a read operation on the plurality of memory blocks to read out data and provide a read enable signal to the memory devices during at least part of an idle time of the channel, which occurs while the read operation is being performed. The plurality of memory devices output first data to the memory controller through the channel in response to the read enable signal, wherein the first data is different from the data previously read out by the read operation that provides the read enable signal in response to the read command.

Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on selected memory cells, among the plurality of memory cells. The control logic controls the read operation of the peripheral circuit in response to a read command that is received from an external device and determines whether to perform a discharge operation of word lines that are connected to the plurality of memory cells based on a type of the read command.

Abstract: Provided herein is a memory device and a storage device including the same. The memory device includes an input/output circuit configured to receive a command, an address, and data from a memory controller. The memory device also includes control logic configured to control a peripheral circuit of the memory device so that an operation of storing the data in a memory cell of the memory device is performed based on the command and the address received from the input/output circuit. The input/output circuit includes a queue layer configured to temporarily store the command and the address and to output the command and the address to the control logic based on at least one of a rising edge and a falling edge of a write enable signal received by the memory device from the memory controller.

Abstract: A storage device having improved performance includes: a plurality of memory devices, each memory device including a plurality of memory blocks, the plurality of memory devices coupled to a channel; and a memory controller coupled to the channel to be in communication with the plurality of memory devices to provide a read command for instructing a read operation on the plurality of memory blocks to read out data and provide a read enable signal to the memory devices during at least part of an idle time of the channel, which occurs while the read operation is being performed. The plurality of memory devices output first data to the memory controller through the channel in response to the read enable signal, wherein the first data is different from the data previously read out by the read operation that provides the read enable signal in response to the read command.

Abstract: A memory system includes a memory device and a memory controller. The memory controller transmits a data read command to the memory device, inputs N read enable toggle signals to the memory device in order for the memory device to output the data requested by the data read command requests, and inputs an additional read enable toggle signal to the memory device. The memory device outputs status information of the memory device to the memory controller in response to the additional read enable toggle signal.

Abstract: Provided herein is a memory device and a storage device including the same. The memory device includes an input/output circuit configured to receive a command, an address, and data from a memory controller. The memory device also includes control logic configured to control a peripheral circuit of the memory device so that an operation of storing the data in a memory cell of the memory device is performed based on the command and the address received from the input/output circuit. The input/output circuit includes a queue layer configured to temporarily store the command and the address and to output the command and the address to the control logic based on at least one of a rising edge and a falling edge of a write enable signal received by the memory device from the memory controller.

Abstract: A memory device includes: a plurality of memory cells; soft read logic configured to generate soft data by reading data from the plurality of memory cells in response to a soft read command from a controller, the soft data including at least a major symbol and at least a minor symbol; a compressor configured to generate compressed data by: encoding, into a code alphabet having a second length, a major source alphabet including repetitions of the major symbol by a first length among a plurality of source alphabets included in the soft data, and encoding, into a code alphabet having a longer length than the second length, a minor source alphabet including repetitions of the major symbol by a shorter length than the first length and ending with one minor symbol; and an interface configured to provide the compressed data to the controller.

Abstract: Provided herein is a semiconductor memory device including a memory cell array, a peripheral circuit, an operation information storage, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a read operation for setup information stored in the memory cell array. The operation information storage may store the setup information. The control logic may control a read operation of the peripheral circuit and a storage operation of the operation information storage. The control logic may control the peripheral circuit and the operation information storage such that a storage section in which the operation information storage stores first setup information and a read section in which the peripheral circuit reads second setup information from the memory cell array are at least partially overlapped with each other.

Abstract: Provided herein is a semiconductor memory device including a memory cell array, a peripheral circuit, an operation information storage, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a read operation for setup information stored in the memory cell array. The operation information storage may store the setup information. The control logic may control a read operation of the peripheral circuit and a storage operation of the operation information storage. The control logic may control the peripheral circuit and the operation information storage such that a storage section in which the operation information storage stores first setup information and a read section in which the peripheral circuit reads second setup information from the memory cell array are at least partially overlapped with each other.

Abstract: An electronic device is provided. The electronic device may include a display module, a bracket disposed on a rear surface of the display module, and a first adhesive member which fixes at least a portion of the display module to the bracket, between the display module and the bracket. The first adhesive member may have adhesive force which is reduced to a specified value or less by at least one of force, light, and/or heat applied from outside.

Abstract: Disclosed are a display and an electronic device including the display, which includes a panel device outputting a specified image using a power applied thereto and an external protective layer having a specified transparency and disposed on the panel device to protect the panel layer. The external protective layer is provided such that a thickness of a center portion of an upper portion surface is greater than a thickness of a peripheral portion, and the panel device includes a panel layer outputting the specified image in response to the power applied thereto and an adhesive layer adhering the panel layer to a lower portion of the external protective layer. Other various embodiments identified in the specification are also possible.

Abstract: An electronic device is provided. The electronic device may include a display module, a bracket disposed on a rear surface of the display module, and a first adhesive member which fixes at least a portion of the display module to the bracket, between the display module and the bracket. The first adhesive member may have adhesive force which is reduced to a specified value or less by at least one of force, light, and/or heat applied from outside.

Abstract: A portable terminal having a long-stroke hinge is disclosed. The portable terminal includes a first main body, a second main body sliding on the first main body, a first member with elasticity having a first end fixed to the first main body and a second end that is horizontally moveable, and a second member having a first end rotatably coupled with the second end of the first member and a second end fixed to the second main body.

Abstract: Provided is a goods information providing terminal that includes an authentication unit authenticating a user based on bio information including a user's fingerprint and initiating a user session when the user is authenticated; a goods information request unit requesting a goods management server that manages goods information and information on the location of goods from a radio frequency identification (RFID) attached to the goods to provide the goods information and the information on the location of the goods; a goods information display unit displaying to the user the goods information or the information on the location of the goods acquired from the goods management server; and a goods processing unit acquiring goods information including how to contact a seller from the goods management server, and contacting an associated agency including the seller when the goods need to be repaired or exchanged.

Abstract: Disclosed herein is a bed mattress and a method of manufacturing the same, in which a permeable reinforcing member is provided at an upper portion and a lower portion of a spring assembly which is one of frame constituents of the bed mattress, and a foaming material is disposed on the permeable reinforcing member so as to be foamed, so that the spring assembly and the foaming material are integrally formed while the foaming material is expanded through fine holes and/or foam expansion holes of the permeable reinforcing member.

Abstract: Disclosed herein is an apparatus for enclosing the exposure wire parts of a spring assembly for a bed mattress which can automate the work process according to the enclosure of the exposure wire parts of a spring assembly, thereby maximizing convenience of the enclosing process and work productivity. According to the inventive apparatus for enclosing exposure wire parts 115a of coil springs 115 in a spring assembly 100 for a bed mattress, the enclosing work of the exposure wire parts protrudingly formed in the spring assembly is performed automatically so that various work loads and the number of work processes according to the enclosing work can be minimized to thereby maximize the work productivity as well as the relevant cost according to the enclosing work is reduced, thereby saving the production cost of the mattress and improving the product competitiveness of the mattress.