Abstract: The present invention relates to a levitating object, and in particular a storage unit is formed such that the levitation height of the levitating object can be adjusted by adjusting the weight of a balance weight placed in the storage unit and the levitation force of the levitating object.

Abstract: The present invention relates to a numeral memory game method capable of memorizing telephone numbers or memorial days stored in a user's portable phone, implementing as a type of a game on the portable phone. A numeral memory game method according to the present invention comprises the steps of generation question data base by extracting at least one of names and telephone numbers stored on an address list of the portable terminal, names and telephone numbers useful for daily life stored on the portable terminal and names and memorial days stored on the portable terminal, extracting the names, telephone numbers and memorial days from the question data base and displaying the names, and the telephone numbers and the memorial days covered partially or entirely on the display part, and comparing the telephone numbers or the memorial days inputted to the input part by a user to them stored on the data base, and determining whether they are identical.

Abstract: The present invention relates to the pharmaceutical composition comprising mainly the guaiacol family compound and the syringol family compounds, extracted from natural plant vinegar. The present invention provides that pharmaceutical compositions has effects of treating oxidative toxicity, regulating blood glucose level, improving blood flow, treating hangover and treating atopic dermatitis as well as the safe composition to be free from acute toxicity, subacute toxicity etc . . . The pharmaceutical composition of the present invention can be used as an agent or an ingredient of health functional food.

Abstract: A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

Abstract: A power amplifier includes drains and sources of a plurality of transistors connected to each other to produce a plurality of common drains and a plurality of common sources, wherein the common drains are connected at a common drain point and wherein the common drain point is connected via an RF choke to a power supply voltage terminal and wherein the common sources are grounded; an output terminal connected to the RF choke; a plurality of bias terminals each coupled via a resistor to the gate of one of the plurality of transistors wherein each of the gates of the plurality of transistors is also capacitively coupled to a radio frequency input.

Abstract: DC offset canceling is disclosed. A DC level fixing signal generator receives feedback input of two output signals from a mixer and generates a level fixing control signal to fix the DC level of the two output signals according to the input values. A DC offset canceling signal generator receives feedback input of two output signals from the mixer and generates offset canceling control signals to cancel the relative difference between the DC levels of the two output signals according to the input values. A DC level fixing and offset canceling circuit fixes the DC level of each of the two output signals from the mixer and cancels the relative difference between the DC levels of the two output signals according to the level fixing control signal and the offset canceling control signals.

Abstract: A quadrature signal generator includes a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop; and a phase corrector that variably controls the capacitance of the variable capacitive elements.

Abstract: A power amplifier includes drains and sources of a plurality of transistors connected to each other to produce a plurality of common drains and a plurality of common sources, wherein the common drains are connected at a common drain point and wherein the common drain point is connected via an RF choke to a power supply voltage terminal and wherein the common sources are grounded; an output terminal connected to the RF choke; a plurality of bias terminals each coupled via a resistor to the gate of one of the plurality of transistors wherein each of the gates of the plurality of transistors is also capacitively coupled to a radio frequency input.

Abstract: DC offset canceling is disclosed. A DC level fixing signal generator receives feedback input of two output signals from a mixer and generates a level fixing control signal to fix the DC level of the two output signals according to the input values. A DC offset canceling signal generator receives feedback input of two output signals from the mixer and generates offset canceling control signals to cancel the relative difference between the DC levels of the two output signals according to the input values. A DC level fixing and offset canceling circuit fixes the DC level of each of the two output signals from the mixer and cancels the relative difference between the DC levels of the two output signals according to the level fixing control signal and the offset canceling control signals.

Abstract: A phase splitter is disclosed for preventing a timing loss from a presentation timing mismatch of a clock signal of a phase equal to a reference signal and a clock signal of a phase inverted from the reference signal, including a semiconductor device for providing a signal of the same phase and a signal of an inverted phase with respect to a received reference signal, the semiconductor device including a first and a second transmission gates for receiving the reference signal and an inverted version of the received reference signal, and a third and a fourth transmission gates for receiving the reference sign, and the inverted version of that reference signal and for generating a signal having the same phase as the received reference signal and for providing that signal at the same time that the first and second transmission gates provide their output signal, the signals output by the first and second transmission gates having the same timing and opposite phase as the signal output by the third and fourth tran

Abstract: A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predertermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.

Abstract: A clock signal phase comparator includes a first delay unit for delaying a clock signal for a predetermined time, a first phase detector for comparing an output signal of the first delay unit and a reference clock signal and outputting a first high or low level output signal, a second delay unit for delaying for a predetermined time and outputting the reference clock signal, and a second phase detector for comparing an output signal of the second delay unit and the clock signal and outputting a second high or low level output signal. The phase comparator separately displays the phase comparison results in grades of fast, slow and locking, and when a locked phase is detected, the phase control system is partially or entirely disabled, for thereby reducing current consumption of the system.

Abstract: A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predetermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.

Abstract: A circuit for detecting leakage voltage of a MOS capacitor, the detecting circuit including a timing control signal generator for generating a timing control signal; a sample/hold circuit for sampling and holding a first voltage, the sample/hold circuit comprising a switching circuit switched by an output of the timing control signal generator and being operatively coupled to a MOS capacitor; a monitoring capacitor for monitoring a leakage voltage of the MOS capacitor operatively coupled to the sample/hold circuit; a monitoring capacitor precharge circuit for holding a second voltage in the monitoring capacitor; and a leakage voltage detecting portion for detecting when a leakage voltage of the monitoring capacitor is below a predetermined value. The leakage voltage detecting portion is also capable of detecting what value the leakage voltage of the monitoring capacitor is, for example, when the leakage voltage is below the predetermined value.

Abstract: A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections.