Abstract: A system-on-chip may include a hard-macro block, a deepstop control logic circuit, and/or a multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit. The deepstop control logic circuit may be configured to transfer data to the hard-macro block from the multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit during a normal mode. The deepstop control logic circuit may be configured to latch the data output from the MTCMOS logic circuit upon an entry into a deepstop mode and interrupt a power supply to the hard-macro block during the deepstop mode.

Abstract: A system-on-chip includes: a controller generating a first input/output control signal determining an input/output state in a normal mode, a second input/output control signal determining the input/output state in a sleep mode, a normal value, and a sleep value; stored in first through fourth registers; a first selector selecting the first or second input/output control signals depending on operation mode; an internal logic circuit operating in the normal mode and generating a signal to be transferred to an external chip based on the normal value; and a second selector selecting an output from the fourth register or the internal logic circuit depending on the operation mode; a power manager controlling the first and second selectors; and a retention input/output device storing outputs of the first and second selectors when the normal mode turns to the sleep mode, which are held when transitioning from the normal to sleep mode.

Abstract: An input/output device includes: a level shifter configured to convert an input signal of a first voltage into an output signal of a second voltage; and an output driver configured to operate in response to the output signal. The level shifter is configured to generate the output signal with a predetermined level when the first voltage is interrupted to supply.

Abstract: A multi-threshold CMOS system and method controls a state of respective blocks individually. Each block includes a logic circuit having a logic transistor and a control transistor connected between the logic circuit and a power line connected to one of a ground and a power source. The control transistor has a higher threshold than the logic transistor. The blocks are controlled by generating an individual block ON/OFF signal for each block, generating an individual control signal in response to the individual block ON/OFF signal, supplying the individual control signal to the control transistor and controlling voltage supply to the logic circuit within each block in accordance with the individual control signal.

Abstract: A system-on-chip includes: a controller generating a first input/output control signal determining an input/output state in a normal mode, a second input/output control signal determining the input/output state in a sleep mode, a normal value, and a sleep value; stored in first through fourth registers; a first selector selecting the first or second input/output control signals depending on operation mode; an internal logic circuit operating in the normal mode and generating a signal to be transferred to an external chip based on the normal value; and a second selector selecting an output from the fourth register or the internal logic circuit depending on the operation mode; a power manager controlling the first and second selectors; and a retention input/output device storing outputs of the first and second selectors when the normal mode turns to the sleep mode, which are held when transitioning from the normal to sleep mode.

Abstract: A system-on-chip may include a hard-macro block, a deepstop control logic circuit, and/or a multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit. The deepstop control logic circuit may be configured to transfer data to the hard-macro block from the multi-threshold complementary metal-oxide-semiconductor (MTCMOS) logic circuit during a normal mode. The deepstop control logic circuit may be configured to latch the data output from the MTCMOS logic circuit upon an entry into a deepstop mode and interrupt a power supply to the hard-macro block during the deepstop mode.

Abstract: An input/output device includes: a level shifter configured to convert an input signal of a first voltage into an output signal of a second voltage; and an output driver configured to operate in response to the output signal. The level shifter is configured to generate the output signal with a predetermined level when the first voltage is interrupted to supply.

Abstract: A multi-threshold CMOS system and method controls a state of respective blocks individually. Each block includes a logic circuit having a logic transistor and a control transistor connected between the logic circuit and a power line connected to one of a ground and a power source. The control transistor has a higher threshold than the logic transistor. The blocks are controlled by generating an individual block ON/OFF signal for each block, generating an individual control signal in response to the individual block ON/OFF signal, supplying the individual control signal to the control transistor and controlling voltage supply to the logic circuit within each block in accordance with the individual control signal.

Abstract: A method of analyzing the morphology of bulk and surface defects on a semiconductor wafer includes: determining a location of the defects; marking an indication proximate the location; milling the wafer using the indication, to thereby make a specimen; and analyzing the specimen to obtain the defects' morphology. Bulk defects as deep 5-250 &mgr;m can be detected and surface defects as deep as 10 &mgr;m from the wafer's surface can be detected. Both morphology analyses preferably include using TEM (Transmission Electron Microscopy). The location determination for both defects preferably includes projecting a laser beam onto the wafer. By obtaining the morphology of the defects, the cause of failure due to the bulk defects and surface defects can accurately be investigated, increasing semiconductor devices' reliability.

Abstract: A wafer packaging method in which a wafer is placed into a packaging bag that is sealed before the concentration of sulphuric oxide on the surface of the wafer reaches 3×1012 atoms/cm2.

Abstract: Compositions useful for polishing wafers to be used in microelectronic devices comprise silicon dioxide, aluminum oxide, sodium hydroxide, and water. Cleaning compositions for removing electron wax from wafers to be used in microelectronic devices comprise from about 2 to about 6 percent by weight of ammonium hydroxide, from about 10 to about 22 percent by weight of hydrogen peroxide, and water.