Patents by Inventor Sung Hun Shin

Sung Hun Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12233601
    Abstract: Provided is a method for creating a 2D slicing polyline based support structure for 3D printing. A method for creating a support structure according to an embodiment of die present invention comprises: slicing a 3D model into a plurality of 2D layers; comparing the 2D layers to calculate a support position for each of the 2D layers; and creating supports at the calculated positions. As a result, the supports can be created at precise and meaningful positions, a stable output is possible, and additional slicing work is not necessary on the created supports, whereby improvement of speed can be expected.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: February 25, 2025
    Assignee: Korea Electronics Technology Institute
    Inventors: Hwa Seon Shin, Hye In Lee, Sung Hwan Chun, Sung Hun Park
  • Patent number: 12220921
    Abstract: Provided is a nozzle clogging defect compensating method for compensating for a nozzle clogging defect appearing in a binder jetting stack manufacturing means. The nozzle clogging defect compensating method according to an embodiment of the present invention comprises the steps of: determining a defect occurrence region when a clogging defect of a nozzle used in the binder jetting stack manufacturing means occurs; determining whether compensation for the detect occurrence region is possible; when the compensation is possible, generating defect information and reflecting the defect information in an output code; setting a defect compensation region on the basis of the defect information; determining a defect compensation type of the defect compensation region; and reflecting a result of the determining in the output code.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: February 11, 2025
    Assignee: Korea Electronics Technology Institute
    Inventors: Hwa Seon Shin, Sung Hun Park, Hye In Lee, Sung Hwan Chun, Jin Min Jang
  • Publication number: 20250045484
    Abstract: A support sink application method for 3D printing heat dissipation analysis is provided. The support sink application method according to an embodiment of the present invention comprises the steps in which: a support sink application system adds a support sink in order to simulate heat dissipation using a support in a state where a support shape is not generated in a 3D model; the support sink application system performs heat dissipation simulation with the support sink added to the 3D model; and the support sink application system adjusts the support sink on the basis of the result of the simulation. Therefore, the convenience of heat dissipation simulation can be improved by introducing the support sink capable of representing heat dissipation by the support with no support shape.
    Type: Application
    Filed: December 14, 2022
    Publication date: February 6, 2025
    Applicant: Korea Electronics Technology Institute
    Inventors: Hwa Seon SHIN, Jae Ho SHIN, Hye In LEE, Sung Hwan CHUN, Sung Hun PARK
  • Patent number: 12202206
    Abstract: Provided are a method and a system for solving a tolerance problem which may occur in a slicing quantization (staircase effect) process of 3D printing which slices a 3D model and laminates layers one by one. According to an embodiment of the present disclosure, a 3D model slicing method includes the steps of: receiving, by a 3D model slicing system, an input of data of a 3D model to 3D print; examining, by the 3D model slicing system, a dimension of a layer thickness of the inputted 3D model; correcting, by the 3D model slicing system, a size of a layer for slicing, based on a result of the examining; and slicing, by the 3D model slicing system, the corrected 3D model. Accordingly, by preserving a dimension within a layer thickness, a problem that a concavo-convex portion is lost in a slicing quantization process of 3D printing according to a slicing position within a layer thickness, and a tolerance occurs is solved.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: January 21, 2025
    Assignee: Korea Electronics Technology Institute
    Inventors: Hwa Seon Shin, Hye In Lee, Sung Hwan Chun, Sung Hun Park
  • Patent number: 12202344
    Abstract: Disclosed is a console operation device including a base plate, at least one solenoid disposed in the base plate, a guide rail disposed in front of the base plate, and a manipulator mounted on the guide rail to move on the guide rail, wherein the at least one solenoid includes a first magnet having a polarity, wherein the manipulator includes a second magnet having a polarity, wherein the manipulator is configured to be moved based on the polarities of the first and second magnets.
    Type: Grant
    Filed: October 11, 2023
    Date of Patent: January 21, 2025
    Assignee: Hyundai Mobis Co., Ltd.
    Inventors: Ji Soo Shin, Tae Hun Kim, Kyung Hoon Kim, Sung Joon Ahn, Shin Jik Lee, Hyun Jun An
  • Publication number: 20250021295
    Abstract: Disclosed herein is a method of controlling, by a voice guidance control device according to some embodiments of the present disclosure, a volume level of personalized voice guidance. The method includes: obtaining information on a distance between an occupant of a vehicle and a seat of the vehicle from a signal generated from the vehicle; and outputting voice guidance related to the occupant. A volume level of the voice guidance is adaptively determined based on the information on the distance between the occupant and the seat.
    Type: Application
    Filed: March 26, 2024
    Publication date: January 16, 2025
    Applicant: HYUNDAI MOBIS CO., LTD.
    Inventors: Tae Hun KIM, Ji Soo SHIN, Myung Bin CHOI, Sung Joon AHN
  • Patent number: 6713336
    Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: March 30, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Hun Shin, Jae Doo Eom
  • Patent number: 6627943
    Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: September 30, 2003
    Assignee: Hynix Semiconductor Inc
    Inventors: Sung Hun Shin, Jae Doo Eom
  • Publication number: 20030164518
    Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.
    Type: Application
    Filed: February 27, 2003
    Publication date: September 4, 2003
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Sung Hun Shin, Jae Doo Eom
  • Publication number: 20030052359
    Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.
    Type: Application
    Filed: December 7, 2001
    Publication date: March 20, 2003
    Inventors: Sung Hun Shin, Jae Doo Eom
  • Patent number: 6391717
    Abstract: There is disclosed a method of manufacturing a flash memory device. In order to solve the problem that the coupling ratio of a gate electrode is low in a stack gate-type flash memory device, the present invention allows a control gate to surround a control gate from its to its bottom. Therefore, the present invention can increase the contact area of the floating gate and the control gate and can also increase the coupling ratio of the gate electrode.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: May 21, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Sung Hun Shin, Byung Hee Cho, Ki Jun Kim