Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: Disclosed are a semiconductor memory device, a controller, a memory system, and an operation method thereof. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: In an aspect of the present invention, it is disclosed a method for receiving a signal in integer-forcing (IF) Multiple-Input Multiple-Output (MIMO) system. The method includes receiving a plurality of reception signal vectors through a plurality of channels, performing an equalization for the plurality of reception signal vectors, performing a decoding for the plurality of reception signals in which the equalization is performed using a plurality of different reversible integer matrixes, and reconstructing a transmission signal from the reception signal in which the decoding is performed.

Abstract: Disclosed are a semiconductor memory device, a controller, and a memory system. The semiconductor memory device includes a memory cell array including a plurality of memory cells, and an error correcting code (ECC) decoder configured to receive first data and a parity output from selected memory cells of the memory cell array. The ECC decoder generates a syndrome based on the first data and the parity, generates a decoding status flag (DSF) indicating a type of an error of the first data by the syndrome, and outputs the second data and the DSF to an external device outside of the semiconductor memory device when a read operation of the semiconductor memory device is performed.

Abstract: In an aspect of the present invention, it is disclosed a method for receiving a signal in integer-forcing (IF) Multiple-Input Multiple-Output (MIMO) system. The method includes receiving a plurality of reception signal vectors through a plurality of channels, performing an equalization for the plurality of reception signal vectors, performing a decoding for the plurality of reception signals in which the equalization is performed using a plurality of different reversible integer matrixes, and reconstructing a transmission signal from the reception signal in which the decoding is performed.

Abstract: The present invention relates to a digital audio amplification device using harmonics and a method thereof, and more specifically, the invention differentially generates characteristics of harmonics (for instance, amplitude or frequency components of harmonics) of an audio signal in order to compensate the audio signal that exceeds a preset threshold value according to the amplitude and characteristics of the audio signal, if the audio signal exceeds the preset threshold value, thereby easily improving the amplitude and the pitch of audio during digital audio amplification.