Abstract: Provided is a method of dynamically controlling power in a multicore environment including a multicore processor which includes a plurality of cores and a scheduler. The method includes determining whether a management policy is set, collecting frequency change information used to change frequencies of the plurality of cores when it is determined that the management policy is set, calculating an average load of each core on a basis of the frequency change information, calculating an average frequency of each core according to the calculated average load of each core, comparing the average frequency of each core and a predetermined threshold value, and setting a next frequency of each core according to the comparison result.

Abstract: A power capping apparatus including a measurement unit to measure a performance counter value and a used amount of power of the computing system before a power limit value is set. A calculation unit to calculate an energy reference value used in an energy conservation mode using the used amount of power and the performance counter value. A management unit to compare a first used amount of power measured before a power limit value is set with the power limit value when the power limit value is set, and limit the used amount of power to a value below the power limit value when the first used amount of power is greater than the power limit value, wherein the management unit outputs an error message so that a user sets the power limit value in which the energy reference value is within an effective range in the energy conservation mode.

Abstract: A method and apparatus for reducing the consumption of standby power through the detection of the idle state of a system are disclosed herein. The apparatus includes a task information acquisition unit, an idle state detection unit, a power reduction determination unit, and a power reduction performance unit. The task information acquisition unit acquires task information from a scheduler. The idle state detection unit detects whether at least one apparatus enters an idle state based on the task information. The power reduction determination unit determines whether to perform the reduction of power consumption of the at least one apparatus based on at least one of an idle counter and the time elapsed after occurrence. The power reduction performance unit performs low-power mode using an apparatus manager corresponding to the at least one apparatus if it is determined that the reduction of power consumption is to be performed.

Abstract: CPU frequency scaling apparatus and method, which can select an optimal frequency based on a preset power versus efficiency table for a CPU when selecting the operating frequency based on the average load of the overall system during a specific time interval. The CPU frequency scaling apparatus includes a table generation unit for generating, for all cores, a power versus efficiency table, based on available frequencies for respective cores and power consumption values depending on loads at each frequency, an average load measurement unit for calculating an average load on all the cores, and a frequency determination unit for searching the power versus efficiency table for an optimal frequency, based on load information calculated by the average load measurement unit and current power consumption of all the cores, and determining a found optimal frequency to be a new operating frequency.

Abstract: Disclosed herein is a timer management apparatus in which contiguous timer interrupts of an operating system run on IT equipment (desktop computers, servers, mobile devices, etc.) are coalesced and processed. Accordingly, the timer management apparatus may minimize interrupt processing load and maximize system idle time, thus improving the standby power saving effect. The proposed timer management apparatus includes a timer addition sub-module unit for adding a new timer to a timer group including one or more timers, a timer deletion sub-module unit for deleting any of the registered timers that is intended to be deleted, and a timer expiration sub-module unit for simultaneously processing timers to be expired through a single interrupt processing operation.

Abstract: A virtual workspace providing server for generating a virtual workspace to be provided to a user through a user terminal in an online software service system includes a virtual workspace portal configured to output a software list including a plurality of pieces of software to be provided through a cloud-based service and generate a virtual workspace constituted of software selected by the user, a software list and statistical information manager configured to collect and manage statistical information including at least one of user evaluation information and information about the number of users selecting the software for each of the plurality of pieces of software, a software lifecycle manager configured to collect pattern information in which the software configured in the virtual workspace is used in the user terminal, and a charging manager configured to charge a use fee for the software used by the user using the pattern information.

Abstract: Disclosed herein is a load balancing apparatus and method. The load balancing apparatus includes a load characteristic analysis unit for analyzing characteristics of a required load upon executing a service requested by a client, a scheduling unit for scheduling the load based on the analyzed characteristics, and a load balancing unit for allocating the load stored in a queue corresponding to the analyzed characteristics to a server group into which servers are grouped for respective characteristics, performing service provisioning, and then allocating the load to an available server.

Abstract: Disclosed are an apparatus for managing power/energy based on time information of policy enforcement including a time information acquiring unit configured to acquire management time information including a start time value, an end time value, a day repetition value, and a date repetition value of a power/energy management action with respect to a management target device desired to manage in power/energy, a time information analysis unit configured to analyze the management time information acquired by the time information acquiring unit and to register a management action event for power/energy management in a timer module, and a power management unit configured to perform an power/energy management action on the management target device by checking occurrence of the management action event and controlling operations of control modules of the management target device, and a method thereof.

Abstract: Provided is a method of dynamically controlling power in a multicore environment including a multicore processor which includes a plurality of cores and a scheduler. The method includes determining whether a management policy is set, collecting frequency change information used to change frequencies of the plurality of cores when it is determined that the management policy is set, calculating an average load of each core on a basis of the frequency change information, calculating an average frequency of each core according to the calculated average load of each core, comparing the average frequency of each core and a predetermined threshold value, and setting a next frequency of each core according to the comparison result.

Abstract: A power capping apparatus including a measurement unit to measure a performance counter value and a used amount of power of the computing system before a power limit value is set. A calculation unit to calculate an energy reference value used in an energy conservation mode using the used amount of power and the performance counter value. A management unit to compare a first used amount of power measured before a power limit value is set with the power limit value when the power limit value is set, and limit the used amount of power to a value below the power limit value when the first used amount of power is greater than the power limit value, wherein the management unit outputs an error message so that a user sets the power limit value in which the energy reference value is within an effective range in the energy conservation mode.

Abstract: A RFID tag having a LED is provided. The RFID tag includes an antenna, a RF processor, a controller, a memory, at least one of LEDs, and a LED switching unit. The RF processor receives and transmits a wireless signal through the antenna, and modulates and demodulates transmitted and received signal and data. The controller analyzes a received data outputted from the RF signal processor and generally controls the RFID tag. The memory stores the received data in response to the controller. The LED switching unit turns on/off at least one of the LEDs in response to the controller.

Abstract: An apparatus for hash cryptography has a hardware structure that is capable of providing both secure hash algorithm (SHA)-1 hash calculation and SHA-256 hash calculation. The apparatus for hash cryptography generates a plurality of first message data corresponding to a plurality of first rounds when the SHA-1 hash calculation is performed and generates a plurality of second message data corresponding to a plurality of second rounds when the SHA-256 hash calculation is performed by using one memory, one first register, one XOR calculator, and one OR calculator, calculates a message digest by the SHA-1 hash calculation by using the plurality of first message data when the SHA-1 hash calculation is performed, and calculates a message digest by the SHA-256 by using the plurality of second message data when the SHA-256 hash calculation is performed.

Abstract: A sensor signal processor apparatus having good characteristics and providing an easy and simple interface for various sensors. The sensor signal processor apparatus includes a current source, a sensor, a ramp integrator, a comparator, and a controller. The current source generates a constant current according to a preset value, and the sensor outputs a sensor voltage using the current from the current source. The ramp integrator generates and outputs an integral voltage according to an input command, and the comparator compares the sensor voltage of the sensor with the integral voltage of the ramp integrator and outputting a result of the comparison. The controller controls the generating and outputting of the integral voltage of the ramp integrator according to the comparison result of the comparator.

Abstract: There are provided a low power SHA-1 hash algorithm apparatus having a low power structure and optimized to a trusted platform module (TPM) applied to a mobile trusted computing environment and a low power keyed-hash message authentication code (HMAC) encryption apparatus using the low power SHA-1 hash algorithm apparatus, the HMAC encryption apparatus including: a key padder padding key data for HMAC algorithm; an XOR operator XOR operating the padded key data and a padding constant; a data connector connecting a text to be encrypted, to data obtained by the XOR operating; a data padder padding the connected data; an SHA-1 hash algorithm part performing an SHA-1 hash algorithm on the padded data; a data selector selecting and applying one of a result of the SHA-1 hash algorithm and the text to be encrypted, to the data connector; and a controller controlling operations of the key padder, data connector, and data padder, a sequence of performing a hash algorithm of the SHA-1 hash algorithm part, and storing a

Abstract: A double-integration signal processing apparatus for pulse width amplification and A/D conversion is provided. The current mode double-integration conversion apparatus includes: a current mode double-integration unit which integrates an input current in a predetermined time interval and outputs an integration voltage; a comparison unit which compares the integration voltage output from the current mode double-integration unit with a predetermined comparison voltage V k and outputs an comparison pulse signal; and a gate logic unit which performs a logic operation by using the comparison pulse signal of the comparison unit and an internal signal and outputs an logic operation pulse signal. Accordingly, the current mode double-integration conversion apparatus can be applied to various sensors.

Abstract: An online development environment server, online marketplace server, an online development environment configuring method, and a developed application providing method are provided.

Abstract: Provided is a sensor signal processor apparatus having good characteristics and providing an easy and simple interface for various sensors. The sensor signal processor apparatus includes a current source, a sensor, a ramp integrator, a comparator, and a controller. The current source generates a constant current according to a preset value, and the sensor outputs a sensor voltage using the current from the current source. The ramp integrator generates and outputs an integral voltage according to an input command, and the comparator compares the sensor voltage of the sensor with the integral voltage of the ramp integrator and outputting a result of the comparison. The controller controls the generating and outputting of the integral voltage of the ramp integrator according to the comparison result of the comparator.

Abstract: Provided is a radio frequency identifier (RFID) tag apparatus and an authentication method thereof. The RFID tag apparatus includes a device, a device recognizing unit, an RF processor, and a controller. The device receives a first signal and outputs a second signal in response to the first signal. The device recognizing unit outputs the first signal to the device in response to control signal and receives the second signal to output n-bit data, where n is an integer greater than 1. The RF processor receives an RF signal and extracts information from the RF signal. The controller outputs the control signal to the device recognizing unit in response to the information and processes the n-bit data in response to the information.

Abstract: A wireless communication medium includes an antenna, an analog signal processor, a digital signal processor, and a central processing unit & logic module. The antenna transmits and receives a signal to and from an external apparatus. The analog signal processor converts an analog signal to a digital signal, and converts a digital signal to an analog signal. The digital signal processor demodulates the digital signal, detects the start and end of data, and generates a first control signal for determining whether data is transmitted to the external apparatus and a second control signal for perceiving the end of data, blocking the reception of data, modulating data, and determining whether modulated data is transmitted to the external apparatus. The central processing unit & logic module processes data received from and transmitted to the external apparatus. Accordingly, an efficiency of processing a RF signal can be improved.

Abstract: A wireless communication medium includes an antenna, an analog signal processor, a digital signal processor, and a central processing unit & logic module. The antenna transmits and receives a signal to and from an external apparatus. The analog signal processor converts an analog signal to a digital signal, and converts a digital signal to an analog signal. The digital signal processor demodulates the digital signal, detects the start and end of data, and generates a first control signal for determining whether data is transmitted to the external apparatus and a second control signal for perceiving the end of data, blocking the reception of data, modulating data, and determining whether modulated data is transmitted to the external apparatus. The central processing unit & logic module processes data received from and transmitted to the external apparatus. Accordingly, an efficiency of processing a RF signal can be improved.