Abstract: Disclosed herein is an apparatus and method for offloading parallel computation tasks. The apparatus inserts requests to execute multiple parallel thread groups into at least one parallel thread group queues, wherein when a preset order of priority exists the requests to execute is inserted into the at least one parallel thread group queues according to the preset order of priority, executes parallel threads of the parallel thread groups using a parallel thread group execution request entry extracted from the parallel thread group queue according to the order of priority, inserts an execution result into an execution result queue when execution of the parallel threads according to an execution sequence scheduled in execution startup routine code is terminated, and checks the execution termination state of the parallel thread groups by checking the execution result queue.

Abstract: A power capping apparatus including a measurement unit to measure a performance counter value and a used amount of power of the computing system before a power limit value is set. A calculation unit to calculate an energy reference value used in an energy conservation mode using the used amount of power and the performance counter value. A management unit to compare a first used amount of power measured before a power limit value is set with the power limit value when the power limit value is set, and limit the used amount of power to a value below the power limit value when the first used amount of power is greater than the power limit value, wherein the management unit outputs an error message so that a user sets the power limit value in which the energy reference value is within an effective range in the energy conservation mode.

Abstract: A method and apparatus for reducing the consumption of standby power through the detection of the idle state of a system are disclosed herein. The apparatus includes a task information acquisition unit, an idle state detection unit, a power reduction determination unit, and a power reduction performance unit. The task information acquisition unit acquires task information from a scheduler. The idle state detection unit detects whether at least one apparatus enters an idle state based on the task information. The power reduction determination unit determines whether to perform the reduction of power consumption of the at least one apparatus based on at least one of an idle counter and the time elapsed after occurrence. The power reduction performance unit performs low-power mode using an apparatus manager corresponding to the at least one apparatus if it is determined that the reduction of power consumption is to be performed.

Abstract: CPU frequency scaling apparatus and method, which can select an optimal frequency based on a preset power versus efficiency table for a CPU when selecting the operating frequency based on the average load of the overall system during a specific time interval. The CPU frequency scaling apparatus includes a table generation unit for generating, for all cores, a power versus efficiency table, based on available frequencies for respective cores and power consumption values depending on loads at each frequency, an average load measurement unit for calculating an average load on all the cores, and a frequency determination unit for searching the power versus efficiency table for an optimal frequency, based on load information calculated by the average load measurement unit and current power consumption of all the cores, and determining a found optimal frequency to be a new operating frequency.

Abstract: Disclosed herein is a timer management apparatus in which contiguous timer interrupts of an operating system run on IT equipment (desktop computers, servers, mobile devices, etc.) are coalesced and processed. Accordingly, the timer management apparatus may minimize interrupt processing load and maximize system idle time, thus improving the standby power saving effect. The proposed timer management apparatus includes a timer addition sub-module unit for adding a new timer to a timer group including one or more timers, a timer deletion sub-module unit for deleting any of the registered timers that is intended to be deleted, and a timer expiration sub-module unit for simultaneously processing timers to be expired through a single interrupt processing operation.

Abstract: Disclosed herein is a load balancing apparatus and method. The load balancing apparatus includes a load characteristic analysis unit for analyzing characteristics of a required load upon executing a service requested by a client, a scheduling unit for scheduling the load based on the analyzed characteristics, and a load balancing unit for allocating the load stored in a queue corresponding to the analyzed characteristics to a server group into which servers are grouped for respective characteristics, performing service provisioning, and then allocating the load to an available server.

Abstract: A power capping apparatus including a measurement unit to measure a performance counter value and a used amount of power of the computing system before a power limit value is set. A calculation unit to calculate an energy reference value used in an energy conservation mode using the used amount of power and the performance counter value. A management unit to compare a first used amount of power measured before a power limit value is set with the power limit value when the power limit value is set, and limit the used amount of power to a value below the power limit value when the first used amount of power is greater than the power limit value, wherein the management unit outputs an error message so that a user sets the power limit value in which the energy reference value is within an effective range in the energy conservation mode.

Abstract: A RFID tag having a LED is provided. The RFID tag includes an antenna, a RF processor, a controller, a memory, at least one of LEDs, and a LED switching unit. The RF processor receives and transmits a wireless signal through the antenna, and modulates and demodulates transmitted and received signal and data. The controller analyzes a received data outputted from the RF signal processor and generally controls the RFID tag. The memory stores the received data in response to the controller. The LED switching unit turns on/off at least one of the LEDs in response to the controller.

Abstract: Provided is a radio frequency identifier (RFID) tag apparatus and an authentication method thereof. The RFID tag apparatus includes a device, a device recognizing unit, an RF processor, and a controller. The device receives a first signal and outputs a second signal in response to the first signal. The device recognizing unit outputs the first signal to the device in response to control signal and receives the second signal to output n-bit data, where n is an integer greater than 1. The RF processor receives an RF signal and extracts information from the RF signal. The controller outputs the control signal to the device recognizing unit in response to the information and processes the n-bit data in response to the information.

Abstract: A RFID tag having a LED is provided. The RFID tag includes an antenna, a RF processor, a controller, a memory, at least one of LEDs, and a LED switching unit. The RF processor receives and transmits a wireless signal through the antenna, and modulates and demodulates transmitted and received signal and data. The controller analyzes a received data outputted from the RF signal processor and generally controls the RFID tag. The memory stores the received data in response to the controller. The LED switching unit turns on/off at least one of the LEDs in response to the controller.

Abstract: The present invention relates to a secure hash algorithm (SHA)-based message schedule operation method, a message compression operation method, and a cryptographic device performing the same. The present invention sequentially performs the message schedule operation by using an adder. Also, a memory for storing operation data input for the message schedule operation is used from a 17th round to store intermediate data generated by the message schedule operation. Further, the message compression operation is sequentially performed by using one adder.

Abstract: A wireless communication medium includes an antenna, an analog signal processor, a digital signal processor, and a central processing unit & logic module. The antenna transmits and receives a signal to and from an external apparatus. The analog signal processor converts an analog signal to a digital signal, and converts a digital signal to an analog signal. The digital signal processor demodulates the digital signal, detects the start and end of data, and generates a first control signal for determining whether data is transmitted to the external apparatus and a second control signal for perceiving the end of data, blocking the reception of data, modulating data, and determining whether modulated data is transmitted to the external apparatus. The central processing unit & logic module processes data received from and transmitted to the external apparatus. Accordingly, an efficiency of processing a RF signal can be improved.

Abstract: Provided is a method of storing data in a non-volatile memory, including generating and storing logs including data to be stored and an address of the non-volatile memory in response to a data-writing request, and comparing addresses of the logs and storing data corresponding to the same page by the unit of page in a corresponding area of the non-volatile memory. The method makes it possible to minimize delay in storing data, reduce the number of accesses to the non-volatile memory and uniformly write data in the whole non-volatile memory, thereby minimizing a response time of the non-volatile memory and increasing the lifetime of the non-volatile memory.

Abstract: Provided are a wireless communication medium and a method for operating the wireless communication medium. The wireless communication medium includes an antenna, an analog signal processor, a digital signal processor, and a central processing unit & logic module. The antenna transmits and receives a signal to and from an external apparatus. The analog signal processor converts an analog signal received via the antenna to a digital signal, and converts a digital signal to be transmitted to the external apparatus to an analog signal and transmits the analog signal to the antenna.

Abstract: Provided is a method of storing data in a non-volatile memory, including generating and storing logs including data to be stored and an address of the non-volatile memory in response to a data-writing request, and comparing addresses of the logs and storing data corresponding to the same page by the unit of page in a corresponding area of the non-volatile memory. The method makes it possible to minimize delay in storing data, reduce the number of accesses to the non-volatile memory and uniformly write data in the whole non-volatile memory, thereby minimizing a response time of the non-volatile memory and increasing the lifetime of the non-volatile memory.

Abstract: A wireless communication medium includes an antenna, an analog signal processor, a digital signal processor, and a central processing unit & logic module. The antenna transmits and receives a signal to and from an external apparatus. The analog signal processor converts an analog signal to a digital signal, and converts a digital signal to an analog signal. The digital signal processor demodulates the digital signal, detects the start and end of data, and generates a first control signal for determining whether data is transmitted to the external apparatus and a second control signal for perceiving the end of data, blocking the reception of data, modulating data, and determining whether modulated data is transmitted to the external apparatus. The central processing unit & logic module processes data received from and transmitted to the external apparatus. Accordingly, an efficiency of processing a RF signal can be improved.

Abstract: A wireless communication medium includes an antenna, an analog signal processor, a digital signal processor, and a central processing unit & logic module. The antenna transmits and receives a signal to and from an external apparatus. The analog signal processor converts an analog signal to a digital signal, and converts a digital signal to an analog signal. The digital signal processor demodulates the digital signal, detects the start and end of data, and generates a first control signal for determining whether data is transmitted to the external apparatus and a second control signal for perceiving the end of data, blocking the reception of data, modulating data, and determining whether modulated data is transmitted to the external apparatus. The central processing unit & logic module processes data received from and transmitted to the external apparatus. Accordingly, an efficiency of processing a RF signal can be improved.