Abstract: A display device includes a display panel including a plurality of pixels, a power supply which provides a driving voltage to the pixels, and a controller which outputs a first signal by comparing a sensing driving current generated by sensing driving currents flowing through the pixels with a limit current, outputs a second signal by comparing a load of previous frame data with a limit load, and outputs a driving voltage control signal for controlling the driving voltage to the power supply based on the first signal and the second signal.

Abstract: A display device includes a display panel including a plurality of pixels, a power supply which provides a driving voltage to the pixels, and a controller which outputs a first signal by comparing a sensing driving current generated by sensing driving currents flowing through the pixels with a limit current, outputs a second signal by comparing a load of previous frame data with a limit load, and outputs a driving voltage control signal for controlling the driving voltage to the power supply based on the first signal and the second signal.

Abstract: A display device includes a display panel including pixels, a luminance controller that divides the display panel into blocks based on coordinate information, calculates a block reference current based on a block current sensed in each of the blocks when reference images are sequentially displayed on the blocks, calculates a target current based on the block reference current and a block load of each of the blocks based on input image data, and calculates a scaling factor based on the target current and a sensing current sensed in each of the blocks when an input image corresponding to the input image data is displayed on the display panel, and a data driver that generates a data voltage corresponding to the input image data and supplies the data voltage to the pixels by adjusting a voltage level of the data voltage based on the scaling factor.

Abstract: A display device includes a display panel divided into a first display area and a second display area in a first direction, a first data driver which provides a first data signal to the first display area through data lines arranged in a second direction crossing the first direction, a second data driver which provides a second data signal to the second display area through the data lines arranged in the second direction, a gate driver which provides a gate signal to the display panel through gate lines arranged in the first direction, a timing controller which generates control signals that control the first data driver, the second data driver, and the gate driver, and a defect detector which controls to display a defect detecting image and a reference image on the first display area and the second display area alternately based on an enable signal.

Abstract: A display device includes a display panel including pixels, a luminance controller that divides the display panel into blocks based on coordinate information, calculates a block reference current based on a block current sensed in each of the blocks when reference images are sequentially displayed on the blocks, calculates a target current based on the block reference current and a block load of each of the blocks based on input image data, and calculates a scaling factor based on the target current and a sensing current sensed in each of the blocks when an input image corresponding to the input image data is displayed on the display panel, and a data driver that generates a data voltage corresponding to the input image data and supplies the data voltage to the pixels by adjusting a voltage level of the data voltage based on the scaling factor.

Abstract: A power voltage generating circuit includes an input part, a clock determining part and a plurality of switches. The input part receives a plurality of clock signals and generates a plurality of peak signals corresponding to rising edges of the plurality of clock signals. The clock determining part determines a normal mode and an abnormal mode based on a number of the plurality of peak signals. The switches blocks outputs of the plurality of clock signals in the abnormal mode.

Abstract: A timing controller of a display device controls a gate driver of the display device. The timing controller includes a clock generator configured to provide a gate clock signal to the gate driver by modulating the gate clock signal with a first modulation pattern in a first frame period and by modulating the gate clock signal with a second modulation pattern different from the first modulation patter in a second frame period.

Abstract: A display device includes a display panel divided into a first display area and a second display area in a first direction, a first data driver which provides a first data signal to the first display area through data lines arranged in a second direction crossing the first direction, a second data driver which provides a second data signal to the second display area through the data lines arranged in the second direction, a gate driver which provides a gate signal to the display panel through gate lines arranged in the first direction, a timing controller which generates control signals that control the first data driver, the second data driver, and the gate driver, and a defect detector which controls to display a defect detecting image and a reference image on the first display area and the second display area alternately based on an enable signal.

Abstract: A display device may include: a plurality of pixels; a gate driver that receives clock signals and generates and applies a plurality of gate signals to a respective plurality of gate lines connected to the plurality of pixels; and a clock signal driver. The clock signal driver may output the clock signals and receive feedback clock signals derived from the clock signals, compare the feedback clock signals, and control amplitudes of the clock signals so that an amplitude difference between the feedback clock signals is less than a threshold.

Abstract: A display apparatus includes a display panel having fan-out lines, data lines, a first dummy line, and a second dummy line. The fan-out lines are sequentially disposed along a first direction. The data lines are connected to the fan-out lines at first through nodes. The first dummy line is connected to one of the nodes. The second dummy line is connected to another of the nodes. A first data driver is configured to output data voltages to some of the fan-out lines based on a data signal. A second data driver is configured to output voltages to other fan-out lines based on the data signal. A timing controller is configured to compensate the data signal based on a voltage of nodes that the dummy lines are connected to.

Abstract: A power voltage generating circuit includes an input part, a clock determining part and a plurality of switches. The input part receives a plurality of clock signals and generates a plurality of peak signals corresponding to rising edges of the plurality of clock signals. The clock determining part determines a normal mode and an abnormal mode based on a number of the plurality of peak signals. The switches blocks outputs of the plurality of clock signals in the abnormal mode.

Abstract: A display device may include: a plurality of pixels; a gate driver that receives clock signals and generates and applies a plurality of gate signals to a respective plurality of gate lines connected to the plurality of pixels; and a clock signal driver. The clock signal driver may output the clock signals and receive feedback clock signals derived from the clock signals, compare the feedback clock signals, and control amplitudes of the clock signals so that an amplitude difference between the feedback clock signals is less than a threshold.

Abstract: A display apparatus includes a display panel which displays an image, a compensation area determiner which divides a display area of the display panel into a compensation area and a normal area, a compensation coefficient determiner which determines a compensation coefficient corresponding to input data of the compensation area, a compensation look up table which stores a noise compensation data which compensates a luminance difference of the compensation area by an interference noise of a light-source driving signal, and a correction data calculator which calculates a correction data corresponding to the input data of the compensation area using the compensation coefficient and the noise compensation data.

Abstract: A display apparatus includes a display panel having fan-out lines, data lines, a first dummy line, and a second dummy line. The fan-out lines are sequentially disposed along a first direction. The data lines are connected to the fan-out lines at first through nodes. The first dummy line is connected to one of the nodes. The second dummy line is connected to another of the nodes. A first data driver is configured to output data voltages to some of the fan-out lines based on a data signal. A second data driver is configured to output voltages to other fan-out lines based on the data signal. A timing controller is configured to compensate the data signal based on a voltage of nodes that the dummy lines are connected to.

Abstract: A method of driving a display panel includes applying a gate signal to a gate line of a display panel to drive the gate line, and driving a data line of the display panel by applying a data signal to the data line, where the driving the data line of the display panel includes over-driving the data line based on a data load signal and a polarity control signal.

Abstract: A display apparatus includes a timing controller configured to output a gate control signal through gate control lines, a gate driver configured to output gate signals in response to the gate control signal provided from the gate control lines, pixels configured to receive data voltages in response to the gate signals, and first and second static electricity prevention parts connected to the gate control lines in parallel configured to discharge a static electricity. Each of the first and second static electricity prevention parts is configured to form current paths, which are smaller in number than a number of the gate control lines, to discharge the static electricity and the static electricity configured to be discharged by the first static electricity prevention part has a polarity different from a polarity of the static electricity configured to be discharged by the second static electricity prevention part.

Abstract: A display apparatus includes a display panel which displays an image, a compensation area determiner which divides a display area of the display panel into a compensation area and a normal area, a compensation coefficient determiner which determines a compensation coefficient corresponding to input data of the compensation area, a compensation look up table which stores a noise compensation data which compensates a luminance difference of the compensation area by an interference noise of a light-source driving signal, and a correction data calculator which calculates a correction data corresponding to the input data of the compensation area using the compensation coefficient and the noise compensation data.

Abstract: A display apparatus includes a timing controller configured to output a gate control signal through gate control lines, a gate driver configured to output gate signals in response to the gate control signal provided from the gate control lines, pixels configured to receive data voltages in response to the gate signals, and first and second static electricity prevention parts connected to the gate control lines in parallel configured to discharge a static electricity. Each of the first and second static electricity prevention parts is configured to form current paths, which are smaller in number than a number of the gate control lines, to discharge the static electricity and the static electricity configured to be discharged by the first static electricity prevention part has a polarity different from a polarity of the static electricity configured to be discharged by the second static electricity prevention part.

Abstract: A display apparatus including a plurality of pixels arranged in association with a plurality of gate lines and a plurality of data lines crossing the gate lines, a data driver configured to drive the data lines, a gate driving unit configured to drive the gate lines in synchronization with a gate control signal, and a timing controller configured to control the data driver and the gate driving unit in response to an image signal and a control signal from an exterior. The timing controller outputs the gate control signal including a plurality of pulses respectively corresponding to the gate lines and an enable time of each pulse of the gate control signal is set according to a position of a corresponding gate line of the gate lines.

Abstract: A display apparatus includes pixels connected to gate lines and data lines crossing the gate lines, a data driver which drives the data lines, a gate driver which drives the gate lines, a timing controller which controls the data driver and the gate driver in response to an image signal and a control signal and outputs a first kickback signal and a second kickback signal, and a voltage generator which outputs a first gate-on voltage and a second gate-on voltage in response to the first and second kickback signals to drive the gate lines. The gate driver drives a first group of gate lines in response to the first gate-on voltage and drives a second group of the gate lines in response to the second gate-on voltage.