Abstract: A display device includes a transistor disposed on a substrate, an organic layer disposed on the transistor and defining grooves, a first pixel electrode disposed on the organic layer, electrically connected to the transistor, and including a pixel metal layer and a pixel protective layer, the pixel protective layer including at least one of an oxide and a halide and surrounding the pixel metal layer, and a dummy electrode disposed on the organic layer, spaced apart from the transistor, and including a dummy metal layer and a dummy protective layer, the dummy protective layer including at least one of an oxide and a halide and surrounding the dummy metal layer.

Abstract: An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

Abstract: An organic light emitting display device may include a substrate, a first pixel electrode on the substrate, a pixel defining layer on the substrate, the pixel defining layer having an opening exposing a portion of the first pixel electrode, a second pixel electrode on the portion of the first pixel electrode exposed by the opening, a hole injection layer on the second pixel electrode, the hole injection layer including a metal oxide, an organic light emitting layer on the hole injection layer; and a common electrode on the organic light emitting layer.

Abstract: An electronic device according to various embodiments may include: a display; an image sensor; and a processor configured to be operatively connected to the display and the image sensor. The processor may be configured to: display a first indicator at a specified position within a preview screen of the image sensor displayed on the display; identify a target on the preview screen; identify a target region corresponding to the identified target among a plurality of candidate target regions including the identified target on the basis of aesthetic scores assigned to the plurality of candidate target regions; display a second indicator corresponding to the identified target region on the preview screen; and when the second indicator is moved to the specified position, generate a photographic image corresponding to the preview screen at a specified time.

Abstract: Disclosed are a negative transconductance device and a multi-valued memory device using the same. The negative transconductance includes a monolithic WSe2 semiconductor thin film; a first doped layer disposed on a first area of the WSe2 semiconductor thin film; a second doped layer disposed on a second area of the WSe2 semiconductor thin film so as to supply holes to the second area, wherein the second area is spaced apart from the first area; a first electrode electrically connected to the first area of the WSe2 semiconductor thin film; a second electrode electrically connected to the second area of the WSe2 semiconductor thin film; and a third electrode for applying a gate voltage to the first area and the second area of the WSe2 semiconductor thin film, and to a third area thereof located between the first and second areas.

Abstract: A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

Abstract: A semiconductor memory device capable of improving performance by the use of a charge storage layer including a ferroelectric material is provided. The semiconductor memory device includes a substrate, a tunnel insulating layer contacting the substrate, on the substrate, a charge storage layer contacting the tunnel insulating layer and including a ferroelectric material, on the tunnel insulating layer, a barrier insulating layer contacting the charge storage layer, on the charge storage layer, and a gate electrode contacting the barrier insulating layer, on the barrier insulating layer.

Abstract: A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

Abstract: In a first aspect of the present disclosure, there is provided a nonvolatile memory device comprising: two electrodes; and a protein switching layer interposed between the two electrodes and including an amino acid, wherein then a voltage is applied to one of the electrodes, the amino acid chelates with an active electrode material to form a conductive filament, wherein the formation of the conductive filament allows a resistance state of the device to vary.

Abstract: The present disclosure provides a multi-functional electronic device with a black phosphorous-based single channel, wherein the device comprises: a black phosphorous-based single channel layer including a horizontal arrangement of a first semiconductor region and a second semiconductor region to define a horizontal junction therebetween, wherein the second semiconductor region has a lower hole-carrier density than the first semiconductor region; a first electrode connected to the first semiconductor region; a second electrode spaced from the first electrode and connected to the second semiconductor region; an ionic gel layer disposed on the first semiconductor region; and a gate electrode for receiving a gate voltage to generate an electric field in the channel layer.

Abstract: In a first aspect of the present disclosure, there is provided a nonvolatile memory device comprising: two electrodes; and a protein switching layer interposed between the two electrodes and including an amino acid, wherein then a voltage is applied to one of the electrodes, the amino acid chelates with an active electrode material to form a conductive filament, wherein the formation of the conductive filament allows a resistance state of the device to vary.

Abstract: The present disclosure provides a multi-functional electronic device with a black phosphorous-based single channel, wherein the device comprises: a black phosphorous-based single channel layer including a horizontal arrangement of a first semiconductor region and a second semiconductor region to define a horizontal junction therebetween, wherein the second semiconductor region has a lower hole-carrier density than the first semiconductor region; a first electrode connected to the first semiconductor region; a second electrode spaced from the first electrode and connected to the second semiconductor region; an ionic gel layer disposed on the first semiconductor region; and a gate electrode for receiving a gate voltage to generate an electric field in the channel layer.

Abstract: A seamless hexagonal h-BN atomic monolayer thin film has a pseudo-single crystal structure including a plurality of h-BN grains that are seamlessly merged. Each of the h-BN grains has a dimension in a range from about 10 ?m to about 1,000 ?m. The seamless hexagonal boron nitride (h-BN) atomic monolayer thin film may be fabricated by a process including pre-annealing a metal thin film at a first temperature in a chamber while supplying hydrogen gas to the chamber; supplying nitrogen source gas and boron source gas to the chamber; and forming the seamless h-BN atomic monolayer thin film having a pseudo-single crystal atomic monolayer structure having a grain dimension in a range from about 10 ?m to about 1,000 ?m by annealing the pre-annealed metal thin film at a second temperature.

Abstract: A seamless hexagonal h-BN atomic monolayer thin film has a pseudo-single crystal structure including a plurality of h-BN grains that are seamlessly merged. Each of the h-BN grains has a dimension in a range from about 10 ?m to about 1,000 ?m.

Abstract: Disclosed is a distribution board for independent microgrid capable of driving a power loads at a remote place such as an island area or a mountainous area etc. with a power generated by using a renewable energy generating device and a diesel generating device using a fossil fuel, preventing a power failure etc. by selectively or successively blocking other loads or unimportant loads among the power loads at need, and stably recovering power supply by preventing an excessive inrush current by successive power supply in a re-driving process.

Abstract: A semiconductor device includes a substrate and a device isolation pattern extending from a surface of the substrate into the substrate. The device isolation pattern has an electrically negative property and a physically tensile property. The device isolation pattern delimits an active region of the substrate. A transistor is provided at the active region and has a channel region formed by part of the active region.

Abstract: An N-type Schottky barrier Source/Drain Transistor (N-SSDT) that uses ytterbium silicide (YbSi2-x) for the source and drain is described. The structure includes a suitable capping layer stack.

Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

Abstract: A method of fabricating an N-type Schottky barrier Source/Drain Transistor (N-SSDT) with ytterbium silicide (YbSi2-x) for source and drain is presented. The fabrication of YbSi2-x is compatible with the normal CMOS process but ultra-high vacuum, which is required for ErSi2-x fabrication, is not needed here. To prevent oxidation of ytterbium during ex situ annealing and to improve the film quality, a suitable capping layer stack has been developed.

Abstract: A photodetector and a method of manufacturing the photodetector are provided. The photodetector comprises a first semiconductor layer; a dielectric layer formed on the first semiconductor layer, the dielectric layer comprising a plurality of openings; a second semiconductor layer formed on the dielectric layer, such that portions of the second semiconductor layer are in contact with the first semiconductor layer at the openings; wherein regions of structural disorder with dislocations exist at interfaces between the first and second semiconductor layers at the openings.