Patents by Inventor Sungju RYU
Sungju RYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954582Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.Type: GrantFiled: December 21, 2022Date of Patent: April 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Sungju Ryu, Hyungjun Kim, Jae-Joon Kim
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Patent number: 11928578Abstract: A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.Type: GrantFiled: December 1, 2020Date of Patent: March 12, 2024Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: Sungju Ryu, Jae-Joon Kim, Youngtaek Oh
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Publication number: 20230362498Abstract: An electronic system may include: a camera to capture a current image; an image processor to generate current image data items; and a splitter circuit to generate first and second images having respective first and second image data items. The splitter circuit splits each current image data item into a first image data item with a first set of bits and a second image data item with a second set of bits distinct from the first set of bits. The first and second image data items correspond to two distinct precisions less than a precision of the current image data items. The electronic system may also include distinct binary neural network circuits to independently process the first and second images to generate first and second processed image data items; and a merger circuit to combine the processed image data items to recover output image data items for display.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Applicant: Postech Research and Business Development FoundationInventors: Hyungjun KIM, Yulhwa KIM, Sungju RYU, Jae-Joon KIM
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Publication number: 20230153181Abstract: Disclosed are electronic devices with predetermined compression schemes for parallel computing and methods thereof. An example electronic device includes cores of one or more processors, one or more memories storing instructions configured to, when executed by the cores, configure the cores to perform operations of an application executed on the electronic device, the operations including communication phases that communicate data between the cores, wherein the application includes, prior to execution of the application on the electronic device, predetermined information associating the communication phases with respective compression schemes, and apply the compression schemes corresponding to the communication phases according to the predetermined information to compress the data of the communication phases that is exchanged between the cores when executing the application.Type: ApplicationFiled: August 26, 2022Publication date: May 18, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Se Hyun YANG, Sungju RYU, Ho Young KIM
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Publication number: 20230131035Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.Type: ApplicationFiled: December 21, 2022Publication date: April 27, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungju RYU, Hyungjun KIM, Jae-Joon KIM
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Patent number: 11562218Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.Type: GrantFiled: May 7, 2020Date of Patent: January 24, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sungju Ryu, Hyungjun Kim, Jae-Joon Kim
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Patent number: 11435981Abstract: An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.Type: GrantFiled: April 14, 2020Date of Patent: September 6, 2022Assignees: SAMSUNG ELECTRONICS CO., LTD., POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: Yonghwan Kim, Wook Kim, Jaejoon Kim, Sungju Ryu
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Publication number: 20210303980Abstract: A method of processing of a sparsity-aware neural processing unit includes receiving a plurality of input activations (IA); obtaining a weight having a non-zero value in each weight output channel; storing the weight and the IA in a memory, and obtaining an input channel index comprising a memory address location in which the weight and the IA are stored; and arranging the non-zero weight of each weight output channel according to a row size of an index matching unit (IMU) and matching the IA to the weight in the IMU comprising a buffer memory storing the input channel index.Type: ApplicationFiled: December 1, 2020Publication date: September 30, 2021Inventors: Sungju RYU, Jae-Joon KIM, Youngtaek OH
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Publication number: 20210064339Abstract: An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.Type: ApplicationFiled: April 14, 2020Publication date: March 4, 2021Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: YONGHWAN KIM, WOOK KIM, JAEJOON KIM, SUNGJU RYU
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Publication number: 20210027142Abstract: Disclosed is a method of operating a neural network system. The method includes splitting input feature data into first splitting data corresponding to a first digit bit and second splitting data corresponding to a second digit bit different from the first digit bit, propagating the first splitting data through a first binary neural network, propagating the second splitting data through a second binary neural network, and merging first result data by propagation of the first splitting data and second result data by propagating the second splitting data to generate output feature data.Type: ApplicationFiled: July 20, 2020Publication date: January 28, 2021Inventors: Hyungjun KIM, Yulhwa KIM, Sungju RYU, Jae-Joon KIM
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Publication number: 20200394504Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.Type: ApplicationFiled: May 7, 2020Publication date: December 17, 2020Applicant: POSTECH Research and Business Development FoundationInventors: Sungju RYU, Hyungjun KIM, Jae-Joon KIM