Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Abstract: On-die control for active interposer voltage regulation according to an example includes receiving, by a switch in voltage regulation circuitry in an active interposer, an input voltage. Voltage regulation control circuitry in a chip die connected to the active interposer controls the voltage regulation circuitry, including causing the switch to couple the input voltage to one or more passive components of the voltage regulation circuitry in the active interposer. The voltage regulation circuitry regulates the input voltage to generate a regulated output voltage that is output to the chip die.

Abstract: Two-stage processor voltage regulation according to an example includes receiving, by a buck switching regulator circuit formed in an active interposer that is positioned on a module, a voltage. The buck switching regulator circuit outputs to each of one or more chip dies positioned on the active interposer based on the received voltage, a first regulated voltage. Each of one or more on-chip voltage regulators in each of the one or more chip dies generates based on the first regulated voltage, a respective second regulated voltage.

Abstract: Global processor core voltage control through integrated voltage regulation includes outputting, from an integrated voltage regulator to a processor core based on a global input voltage, a regulator output voltage. A power efficiency monitor and control circuit receives voltage control parameters from the integrated voltage regulator. The power efficiency monitor and control circuit controls a global voltage regulator based on the received voltage control parameters to cause an adjustment to the global input voltage.

Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Abstract: An integrated circuit and a cable interconnect interface are disposed on a substrate and in communication with one another. The cable interconnect interface includes a first plurality of connector pads arranged in a first column and a second plurality of connector pads arranged in a second column. A radio frequency absorption layer is disposed on one or more of the first plurality of connector pads and the second plurality of connector pads. The first plurality of connector pads includes a first group of transmission connector pads and a first group of receiving connector pads. The second plurality of connector pads includes a second group of transmission connector pads and a second group of receiving connector pads. The first group of transmission connector pads is opposite the second group of transmission connector pads, and the first group of receiving connector pads is opposite the second group of receiving connector pads.

Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Abstract: An apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. The array of micro-bumps includes a plurality of subarrays of micro-bumps. Micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. The apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. The card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. In some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.

Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

Abstract: Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.

Abstract: Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Abstract: A printed circuit board (‘PCB’) including a substrate integrated waveguide (‘SIW’) formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.

Abstract: Methods and apparatuses for vertically transitioning signals between substrate integrated waveguides within a multilayered printed circuit board (PCB) are disclosed. A first substrate integrated waveguide (SIW) is provided in a first layer of the PCB, the first SIW having a first terminal portion. A second SIW is provided in a second layer of the PCB, the second SIW having a second terminal portion that overlaps with the first terminal portion, wherein a first ground plane separates the first SIW and the second SIW. A vertical transition comprising an aperture in the first ground plane that is disposed in an area defined by the overlap of the first terminal portion and the second terminal portion, such that a signal propagated in the first SIW transitions to the second SIW in a different layer through the aperture.

Abstract: A printed circuit board (‘PCB’) including a substrate integrated waveguide (‘SIW’) formed using two ground planes representing the top and bottom walls of the waveguide, tightly pitched ground vias to act as two side walls and two back walls, and a pair of monopole antennas placed at each end of the SIW acting as signal feeding/receiving structures is disclosed. The waveguide dominant mode cut off frequency is determined by the spacing between the two side walls. Within each monopole antenna pair, the first monopole antenna operates at a first frequency while the second monopole antenna operates at another frequency. For each monopole antenna pair, the first monopole antenna and the second monopole antenna are located in the SIW at a distance from the back wall optimal for each operating frequency.

Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.

Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.