Abstract: A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.

Abstract: A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.

Abstract: An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.

Abstract: Circuits, methods, and apparatus for output devices having parasitic transistors for a higher output current drive. One such MOS output device includes a parasitic bipolar transistor that assists output voltage transitions. The parasitic transistor may be inherent in the structure of the MOS device. Alternately, one or more regions, such as implanted or diffused regions, may be added to the MOS device to form or enhance the parasitic bipolar device. The parasitic transistor is turned on when during an appropriate output transition and turned off once the transition is complete. The parasitic device may be turned on by injecting current into the bulk of a pull-down device, by pulling current out of the bulk of a pull-up device, or by tying the bulk of the output device to an appropriate voltage, such as VCC for a pull-down device or ground for a pull-up device.

Abstract: A semiconductor device and method for electrostatic discharge protection. The semiconductor device includes a first semiconductor controlled rectifier and a second semiconductor controlled rectifier. The first semiconductor controlled rectifier includes a first semiconductor region and a second semiconductor region, and the second semiconductor controlled rectifier includes the first semiconductor region and the second semiconductor region. The first semiconductor region is associated with a first doping type, and the second semiconductor region is associated with a second doping type different from the first doping type. The second semiconductor region is located directly on an insulating layer.

Abstract: An ESD device invention comprises first and second transistors formed in a substrate, each having a source, a drain and a gate, the source and drain of the first transaction being connected between ground and an I/O pin or input, the gate of the first transistor being connected to ground and the source and drain of the second transistor being connected between the substrate of the first transistor and the I/O pin or input; first and second capacitors connected in series between ground and the I/O pin or input; and at least a third transistor connected between ground and a node between the first and second capacitors to which the gate of the second transistor is also connected.

Abstract: An integrated circuit is disclosed comprising at least one I/O pull-down device for protecting I/O logic circuits from electrostatic discharge (ESD). The turn-on voltage of the parasitic bipolar transistor in the I/O pull-down device is lowered by forming under a portion of the lightly doped drain (LDD) region of a first conductivity type of a conventional MOS transistor a second region of a second conductivity type. A P-N junction is formed between the second region and the source/drain regions. The turn-on voltage of the parasitic bipolar transistor in the I/O pull-down device can be reduced by at least 3 volts from that of a comparable device that does not practice the invention and can be varied by varying the concentration of the dopant. A method for forming the circuit including a process for recovering the current of the I/O pull-down device and its advantages are also disclosed.

Abstract: Techniques are provided for monitoring the performance of circuits and replacing low performing circuits with higher performing circuits. A frequency detector compares the frequency of a first periodic signal to the frequency of a second periodic signal. The difference in the frequency between the first periodic signal and the second periodic signal indirectly indicates how much the threshold voltages of the transistors have shifted. The difference in frequency between the two periodic signals can be monitored to determine the speed and performance of circuits on the chip. The output of the frequency detector can also indicate when to replace low performing circuits with higher performing circuits. When the frequency of the second periodic signal differs from the frequency of the first periodic signal by a predefined percentage, a low performing circuit is replaced with a higher performing replica circuit.

Abstract: A voltage converter includes a first N-channel MOSFET transistor, an inverter, a plurality of serially-connected diodes and a second N-channel MOSFET transistor. The inverter is coupled to the gate of the first N-channel MOSFET transistor to turn on/off the voltage converter. The anode of the diodes is coupled to the source of the first N-channel MOSFET transistor and the cathode of the diodes are coupled to the drain of the second N-channel MOSFET transistor. Since the source of the second N-channel MOSFET transistor is ground, the voltage clamped at the source of the first N-channel MOSFET transistor is not higher than 3.4V when a high voltage applied to the gate of the second N-channel MOSFET transistor turns it on.

Abstract: Voltage regulator circuitry is provided that produces a stable programming-voltage on a programmable integrated circuit. The programmable integrated circuit has programming control circuitry that provides logic-level programming signals. A controllable voltage supply increases the strength of the logic-level programming signals to produce programming-voltage-level programming signals. The programming-voltage-level programming signals are used to program programmable elements such as flash transistors on the programmable integrated circuit. A temperature-insensitive diode-based voltage feedback circuit is connected to the output of the controllable voltage supply. The voltage feedback circuit provides a corresponding feedback voltage to the controllable voltage supply that the controllable voltage supply used to stabilize the magnitude of the programming-voltage-level programming signals.

Abstract: Integrated circuit standby power consumption may be reduced using a reverse-bias transistor control arrangement that reduces transistor leakage current. Integrated circuit transistors may be turned off using a reverse bias voltage rather than a ground voltage. A charge pump circuit on the integrated circuit may be used to generate the reverse bias voltage. The reverse bias voltage may also be provided from an external source. The integrated circuit may be a programmable logic device in which logic is configured by providing programming data to configuration cells. The configuration cells may be used to apply either a positive power supply voltage to a given transistor to turn that transistor on or to provide the reverse bias voltage to that transistor to turn that transistor off.

Abstract: Integrated circuits are stabilized by monitoring changes that affect circuit operation and by compensating for those changes using power supply adjustments. Changes in operating temperature and threshold voltage changes may be measured. Differential measurements may be made in which threshold voltages measured in continuously-biased monitoring circuits are compared to threshold voltages measured in intermittently-biased monitoring circuits. Temperature changes may be monitored using a temperature monitoring circuit based on an adjustable current source and a diode. Monitoring and compensation circuitry on the integrated circuits may use analog-to-digital and digital-to-analog converters controlled by a control unit to make temperature and threshold voltage measurements and corresponding compensating changes in power supply voltages.

Abstract: An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.

Abstract: An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.

Abstract: Four electric field containment regions are formed in a semiconductor substrate by implanting ions into the substrate along four axes that are angularly oriented about a normal to a surface of the substrate in four orthogonal directions respectively. The implant axes are further angularly tilted from the normal by a large angle on the order of 45.degree. such that the axes intersect the normal at a point below the surface. A field effect transistor (FET) is formed in the substrate above the containment regions such that the FET is substantially centered about the normal and has a channel that is aligned with one of the four orthogonal directions. A source and drain are formed at opposite ends of the channel. The containment regions formed under the source and drain respectively are configured to contain electric fields extending therefrom and thereby suppress punchthrough. The four containment regions are implanted at angles that minimize channeling, and any channeling that does occur is symmetrical.