Patents by Inventor Sung-Kwan Choi
Sung-Kwan Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240081001Abstract: A display device includes a display panel having a folding axis extending in a first direction; and a panel supporter disposed on a surface of the display panel. The panel supporter includes a first layer including a first base resin and first fiber yarns extending in the first direction and dispersed in the first base resin, a second layer disposed on the first layer, the second layer including a second base resin and second fiber yarns extending in a second direction intersecting the first direction and dispersed in the second base resin, and a third layer disposed on the second layer, the third layer including a third base resin and third fiber yarns extending in the first direction and dispersed in the third base resin.Type: ApplicationFiled: May 1, 2023Publication date: March 7, 2024Applicant: Samsung Display Co., LTD.Inventors: Soh Ra HAN, Yong Hyuck LEE, Hong Kwan LEE, Hyun Jun CHO, Min Ji KIM, Sung Woo EO, Eun Gil CHOI, Sang Woo HAN
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Patent number: 9349633Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.Type: GrantFiled: December 8, 2014Date of Patent: May 24, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Ik Kim, Sung-Eui Kim, Hyoung-Sub Kim, Sung-Kwan Choi
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Publication number: 20150162335Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.Type: ApplicationFiled: December 8, 2014Publication date: June 11, 2015Inventors: Dae-Ik KIM, Sung-Eui KIM, Hyoung-Sub KIM, Sung-Kwan CHOI
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Patent number: 8884340Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.Type: GrantFiled: November 17, 2011Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Gyo-Young Jin, Hyeong-Sun Hong, Yong-Chul Oh, Yoo-Sang Hwang, Sung-Kwan Choi, Dong-Soo Woo, Hyun-Woo Chung
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Patent number: 8492832Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.Type: GrantFiled: August 10, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-young Kim, Gyo-young Jin, Hyeong-sun Hong, Yoo-sang Hwang, Sung-kwan Choi, Hyun-woo Chung
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Publication number: 20130037882Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.Type: ApplicationFiled: August 10, 2012Publication date: February 14, 2013Inventors: Ji-young Kim, Gyo-young Jin, Hyeong-sun Hong, Yoo-sang Hwang, Sung-kwan Choi, Hyun-woo Chung
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Publication number: 20120299090Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.Type: ApplicationFiled: November 17, 2011Publication date: November 29, 2012Inventors: Ji-Young Kim, Gyo-Young Jin, Hyeong-Sun Hong, Yong-Chul Oh, Yoo-Sang Hwang, Sung-Kwan Choi, Dong-Soo Woo, Hyun-Woo Chung
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Patent number: 5877463Abstract: A shuttle switch assembly for performing both functions of shuttle and mode is disclosed. The assembly comprises a circuit board. A main base is formed on the circuit board. The main base has a stator protrusively formed at the inner center of the main base and a shuttle axis rotatably formed around the stator. A holder is inserted in the shuttle axis and the holder is provided with a guiding hole having a predetermined length at a side of a periphery of the holder. A dome plate includes a plurality of dome switches on an upper side of the dome plate and the dome plate is installed on the holder; a guiding bracket positioned on an upper portion of the dome plate. The guiding bracket is combined with the holder and is provided with holes which correspond to the dome switches on the dome plate. A shuttle knob is combined with the guiding bracket and is provided with contacting apparatus on a bottom of the shuttle knob.Type: GrantFiled: December 27, 1995Date of Patent: March 2, 1999Assignee: Daewood Electronics Co., Ltd.Inventor: Sung-Kwan Choi
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Patent number: 5495290Abstract: A view finder of a video camera is provided with a lens for enlarging the picture; a housing accommodating the lens therewithin; an eye cup mounted to the housing; and a shield detachably mounted to the eye cup for preventing a contaminant from flowing into the view finder. The shield fits into a camera lens cap of the video camera having one or more pairs of protrusions while video camera is in use. Further, the shield engaged with the camera lens cap is mounted to a holder attached to a handle of the video camera.Type: GrantFiled: October 26, 1994Date of Patent: February 27, 1996Assignee: Daewoo Electronics Co., Ltd.Inventor: Sung-Kwan Choi