Abstract: A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.

Abstract: Provided is a semiconductor device including: a substrate; a first fin-field effect transistor comprising a first fin-type semiconductor layer having a first height and a first width, formed on the substrate; and a second fin-field effect transistor comprising a second fin-type semiconductor layer having a second height and a second width, formed on the substrate. The first fin-field effect transistor and the second fin-field effect transistor are separated by a predetermined distance. The first height is greater than the second height and the first width is less than the second width.

Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulation layer pattern on a substrate, forming a sacrificial layer including impurities on the gate insulation layer pattern, annealing the sacrificial layer so that the impurities in the sacrificial layer diffuse into the gate insulation layer pattern, removing the sacrificial layer, and forming a gate electrode on the gate insulation layer pattern.

Abstract: Methods of manufacturing a semiconductor device include forming a thin layer on a substrate including a first region and a second region and forming a gate insulating layer on the thin layer. A lower electrode layer is formed on the gate insulating layer and the lower electrode layer disposed in the second region is removed to expose the gate insulating layer in the second region. Nitrogen is doped into an exposed portion of the gate insulating layer and the thin layer disposed under the gate insulating layer. An upper electrode layer is formed on the lower electrode layer remaining in the first region and the exposed portion of the gate insulating layer. The upper electrode layer, the lower electrode layer, the gate insulating layer and the thin layer are partially removed to form first and second gate structures in the first and second regions. The process may be simplified.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulation layer pattern on a substrate, forming a sacrificial layer including impurities on the gate insulation layer pattern, annealing the sacrificial layer so that the impurities in the sacrificial layer diffuse into the gate insulation layer pattern, removing the sacrificial layer, and forming a gate electrode on the gate insulation layer pattern.

Abstract: A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.

Abstract: Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

Abstract: A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.

Abstract: Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure.

Abstract: A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, preliminary isolation regions having protruded upper portions are formed on a substrate to define an active region. After an insulation layer is formed on the active region, a first conductive layer is formed on the insulation layer. The protruded upper portions of the preliminary isolation regions are removed to form isolation regions on the substrate and to expose sidewalls of the first conductive layer, and compensation members are formed on edge portions of the insulation layer. The compensation members may complement the edge portions of the insulation layer that have thicknesses substantially thinner than that of a center portion of the insulation layer, and may prevent deterioration of the insulation layer. Furthermore, the first conductive layer having a width substantially greater than that of the active region may enhance a coupling ratio of the semiconductor device.

Abstract: A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

Abstract: A method of manufacturing a non-volatile memory device, includes forming a tunnel isolation layer comprising an oxynitride on a substrate by a simultaneous oxidation and nitridation treatment in which an oxidation process and a nitridation process are simultaneously performed using a processing gas including oxygen and nitrogen. The method further includes performing first and second heat treatments to remove defect sites from the tunnel isolation layer in gas atmospheres including nitrogen (N) and chlorine (Cl), respectively and forming a gate structure on the tunnel isolation layer after the second heat treatment, and forming source/drain regions at surface portions of the substrate adjacent to the gate structure.

Abstract: A semiconductor device includes a semiconductor substrate having a surface, buried isolation regions protruding from the surface of the semiconductor substrate, and a first insulating layer on the surface of the semiconductor substrate between the isolation regions and including a fluorine, nitrogen, and/or heavy hydrogen impurity. A floating electrode is on the first insulating layer, a second insulating layer is on the floating electrode and the isolation regions, and a control gate electrode is on the second insulating layer. Related methods of forming semiconductor devices are also disclosed.