Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode, and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell surrounding at least a portion of the core, and a second shell surrounding at least a portion of the first shell, and a concentration of a rare earth element included in the second shell is more than 1.3 times to less than 3.8 times a concentration of a rare earth element included in the first shell.

Abstract: A display device may include: a substrate including a display area and a non-display area; and pixels in the display area, and each including sub-pixels. Each sub-pixel may include a pixel circuit layer, and a display element layer including at least one light emitting element. The display element layer may include: a first electrode on the pixel circuit layer; a second electrode on the first electrode and electrically insulated from the first electrode; the light emitting element including a first end portion coupled to the first electrode and a second end portion coupled to the second electrode, and between the first electrode and the second electrode; an intermediate layer enclosing at least one area of the light emitting element, and on the first electrode; a connection line electrically connected to the second electrode. The second electrode may be on the intermediate layer.

Abstract: A display device comprises a first electrode, a second electrode disposed to be spaced apart from the first electrode and face the first electrode, a first insulating layer disposed to cover the first electrode and the second electrode, a second insulating layer disposed on at least a part of the first insulating layer and exposing at a part of a region where the first electrode and the second electrode overlaps the first insulating layer and at least one light emitting element on the exposed first insulating layer between the first electrode and the second electrode, wherein the second insulating layer includes at least one opening exposing the first insulating layer and disposed to be spaced apart from each other on a region where the first electrode and the second electrode face each other, and a bridge portion between the openings, and the light emitting element is disposed on the opening.

Abstract: The present disclosure relates to a simulation apparatus for secondary battery production.

Abstract: A battery pack includes a sub-pack including a plurality of battery modules that are located adjacent to one another; a duct coupled to a side of the sub-pack in a width direction of the sub-pack; and a duct cover covering a duct opening portion formed on a side of the duct in a longitudinal direction of the duct, the duct cover including a filter having a mesh structure.

Abstract: A battery module includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack and a pair of side plates covering both side portions of the cell stack; a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing; and a plurality of spark delay portions protruding from an inner surface of each of the pair of side plates and spaced apart from one another in a height direction of the side plate.

Abstract: A battery module ac includes a cell stack in which a plurality of battery cells are vertically stacked; a module housing including a base plate supporting the cell stack, and a pair of side plates covering both side portions of the cell stack and each including a spark direction changing portion formed by bending an end portion of the side plate in a longitudinal direction of the side plate toward the cell stack; and a bus bar frame assembly covering an opening portion formed on a side of the module housing in a longitudinal direction of the module housing, the bus bar frame assembly including a bus bar frame coupled to a side of the cells tack in a longitudinal direction of the cell stack and a bus bar located on the bus bar frame and coupled to an electrode lead of the battery cell.

Abstract: A display device includes a first electrode and a second electrode that are spaced apart from and facing each other; a light-blocking layer disposed above the first electrode and the second electrode; and at least one light-emitting element disposed between the first electrode and the second electrode. The light-blocking layer includes a light-blocking portion absorbing light and an opening pattern. The light-blocking portion includes an area partially overlapping the first electrode and the second electrode. The at least one opening pattern exposes portions of the first and second electrodes facing each other and at least a portion of an area between the first and second electrodes facing each other. The at least one light-emitting element overlaps the at least one opening pattern.

Abstract: A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.

Abstract: Disclosed are program and read methods for a nonvolatile memory system, including determining to program first data in which one of fast and normal modes; providing the first data with an error code generated by a multi-bit ECC engine, in the fast mode, and generating second data; programming the second data in a cell array by a program voltage having a second start level higher than a first start level; and reading the second data from the cell array, the second data being output after processed by the multi-bit ECC engine that detects and corrects an error from the second data.

Abstract: Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit. Related methods are also disclosed.

Abstract: A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.

Abstract: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

Abstract: A memory system is provided which includes a host, a flash memory device, and a dual port memory which exchanges data with the host and the flash memory device. The flash memory device utilizes a portion of the dual port memory as a working memory.

Abstract: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

Abstract: A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

Abstract: A sense amplifier circuit for a flash memory device is disclosed. The sense amplifier including a first transistor controlled by a first voltage applied via a selected bit line, and a second transistor controlled by a second voltage applied via an unselected bit line. The second transistor has a current driving capability lower than a current driving capability of the first transistor.

Abstract: Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit. Related methods are also disclosed.

Abstract: Disclosed are program and read methods for a nonvolatile memory system, including determining to program first data in which one of fast and normal modes; providing the first data with an error code generated by a multi-bit ECC engine, in the fast mode, and generating second data; programming the second data in a cell array by a program voltage having a second start level higher than a first start level; and reading the second data from the cell array, the second data being output after processed by the multi-bit ECC engine that detects and corrects an error from the second data.

Abstract: A memory system is provided which includes a host, a flash memory device, and a dual port memory which exchanges data with the host and the flash memory device. The flash memory device utilizes a portion of the dual port memory as a working memory.