Abstract: Example embodiments are directed to a semiconductor package for improving Signal Integrity (SI) characteristics. The semiconductor package includes a package substrate, a mediate substrate arranged on the package substrate and including an active layer and a wiring layer, and at least two semiconductor devices on the mediate substrate. The wiring layer includes path wirings configured to connect the at least two semiconductor devices to each other. The path wirings include n paths (n is an integer that is 2 or more), and the active layer includes a selection circuit configured to select one of the n paths.

Abstract: A memory package may include a first memory die including: a first substrate; a first wiring layer on a first surface of the first substrate, the first surface being a first active surface; and a first bonding pad on the first wiring layer. The memory package may further include a second memory die including: a second substrate on the first memory die; a second wiring layer between the first surface of the first substrate and a second surface of the second substrate, the second surface being a second active surface; and a second bonding pad on the second wiring layer and electrically connected to the first bonding pad. The memory package may further include a package substrate including a first wire pad electrically connected, by a first wire, to the first bonding pad and the second bonding pad.

Abstract: A semiconductor package includes a package substrate, a bridge chip structure including a plurality of bridge chips that are accommodated in the package substrate and stacked in a vertical direction, and a plurality of semiconductor chips that are arranged on the package substrate and are electrically connected to each other through the bridge chip structure, wherein each of the plurality of bridge chips has different sizes.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: A package substrate includes: a build-up structure; and a core layer disposed on the build-up structure, wherein the build-up structure includes: a signal ball pad; an interconnection member disposed on the signal ball pad; a signal connection pad disposed on the interconnection member; and a plurality of signal vias and a plurality of signal lines alternately arranged in a vertical direction on the signal connection pad, wherein the interconnection member has a first height in the vertical direction, wherein each of the plurality of signal vias has a second height in the vertical direction, and wherein the first height is greater than the second height.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: A package substrate may include a core layer, a first line layer on a lower surface of the core layer and including multiple layers of first lines, and a second line layer on an upper surface of the core layer and including multiple layers of second lines. The core layer may include a core body and a core via. The core via may penetrate the core body and extend in a vertical direction. A first signal line of the first lines may be connected to a second signal line of the second lines through the core via. The first signal line may be arranged in a form of an inductor in the first line layer.

Abstract: A semiconductor package including: a substrate that includes a wiring line; and a 3-dimensional integrated circuit structure on the substrate, the 3-dimensional integrated circuit structure including a first die and a second die on the first die, the first die including a first capacitor structure having a defect, a second capacitor structure free of defects, and a plurality of through silicon vias connected to the second die, wherein the first capacitor structure is electrically separated from the second die, and the second capacitor structure is electrically connected to a corresponding through silicon via among the plurality of through silicon vias through the wiring line.

Abstract: A semiconductor package includes a package substrate including a first voltage substrate wire, an interposer substrate provided on the package substrate and including a first voltage interposer wire, a first semiconductor chip mounted on a top surface of the interposer substrate, and a voltage control chip provided on the top surface of the interposer substrate and laterally spaced apart from the first semiconductor chip, wherein the first semiconductor chip is electrically connected to the voltage control chip through the first voltage substrate wire, and wherein the first semiconductor chip is electrically connected to the voltage control chip through the first voltage interposer wire.

Abstract: Disclosed is a memory device, which includes a logic circuit that receives a first signal and a second signal from an external host, an output circuit that receives a first logic operation result or a second logic operation result from the logic circuit, a first logic gate that receives the first signal or the second signal and performs a third logic operation to output a third signal, a second logic gate that receives the first signal and the second signal and performs a fourth logic operation to output a fourth signal, and a multiplexer that receives the third signal and the fourth signal, receives the first logic operation result or the second logic operation result from the output circuit, and outputs one of the third signal and the fourth signal as a fifth signal in response to the first or second logic operation results.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.

Abstract: Disclosed is a memory device, which includes a buffer die that outputs a first power supply voltage to a first through-substrate via (e.g., through-silicon via (TSV)) and receives a small swing data signal from a second TSV generated based on the first power supply voltage, and a core die that is electrically connected to the buffer die through the first and second TSVs, includes a first cell capacitor electrically connected to the first TSV and configured to block a first noise introduced to the first power supply voltage received through the first TSV. The core die outputs the small swing data signal to the second TSV.

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

Abstract: Disclosed is a memory device, which includes a buffer die that outputs a first power supply voltage to a first through-substrate via (e.g., through-silicon via (TSV)) and receives a small swing data signal from a second TSV generated based on the first power supply voltage, and a core die that is electrically connected to the buffer die through the first and second TSVs, includes a first cell capacitor electrically connected to the first TSV and configured to block a first noise introduced to the first power supply voltage received through the first TSV. The core die outputs the small swing data signal to the second TSV.

Abstract: A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

Abstract: The present invention relates to metal salts of 3-methyl-chromane or thiochromane derivatives, stereoisomers or hydrates thereof, and an anti-estrogenic pharmaceutical composition which comprises the above compound as an active component and exhibits a highly improved solubility.

Abstract: A compound having the following general formula (1): in which R1 represents an ethyl group, etc.; R2 represents a hydrogen atom, etc.; R3 represents a C1-C5 perhalogenoalkyl group, etc.; each of R4 and R5 independently represents a hydrogen atom, etc.; X represents an oxygen atom or a sulfur atom; m represents an integer of 2 to 14; and n represents an integer of 2 to 7; or an enantiomer of the compound, or a hydrate or a pharmaceutically acceptable salt of the compound or its enantiomer is advantageous in pharmaceutical use because of its anti-estrogenic activity.