Abstract: In a method of designing a mask, a first mask including an active region, a gate structure, and a gate tap partially overlapping the active region and the gate structure is designed. The first mask is changed so that a portion of the gate tap is extended. An OPC is performed on the changed first mask to design a second mask.

Abstract: In a method of designing a mask, a first mask including an active region, a gate structure, and a gate tap partially overlapping the active region and the gate structure is designed. The first mask is changed so that a portion of the gate tap is extended. An OPC is performed on the changed first mask to design a second mask.

Abstract: Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.

Abstract: In a retarget process modeling method, an effect according to density of patterns, and shapes or distances with respect to neighboring patterns may be sufficiently reflected while a relatively small amount of time and few costs are consumed. The retarget process modeling method involves obtaining prediction data, by a modelling calculating unit, on a test layout using a first process model, obtaining bias data based on measurement data of the test layout and the prediction data, using the bias data to check and detect corresponding features of a representative pattern affected by a photoresist (PR) flow rate, generating kernels including a PR flow kernel in consideration of a sub resolution assist feature (SRAF) pattern of the representative pattern to determine an uncalibrated model including the kernels and obtaining a second process model by fitting the uncalibrated model to the measurement data to obtain a second process model.

Abstract: Provided are a compensating mask, a multi-optical system using the compensating mask, and a method of compensating for a 3-dimensional (3-D) mask effect using the compensating mask. Methods of compensating for a 3-D mask effect using a compensating mask may include generating a first kernel corresponding to a normal mask used for forming a minute pattern, generating a second kernel corresponding to a compensating mask, mixing the first kernel corresponding to the normal mask with the second kernel corresponding to the compensating mask, and generating a multi-optical system kernel corresponding to mixing the first kernel and the second kernel.

Abstract: Provided are a compensating mask, a multi-optical system using the compensating mask, and a method of compensating for a 3-dimensional (3-D) mask effect using the compensating mask. Methods of compensating for a 3-D mask effect using a compensating mask may include generating a first kernel corresponding to a normal mask used for forming a minute pattern, generating a second kernel corresponding to a compensating mask, mixing the first kernel corresponding to the normal mask with the second kernel corresponding to the compensating mask, and generating a multi-optical system kernel corresponding to mixing the first kernel and the second kernel.

Abstract: An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models.

Abstract: Design rules for circuit patterns of a semiconductor device are identified, and schematic layouts of the circuit patterns are generated according to the design rules. Lithography friendly layout (LFL) circuit patterns are generated from the schematic layouts. Target layout circuit patterns are generated from the LFL circuit patterns. Optical proximity effect correction (OPC) is performed on the target layout circuit patterns to generate OPC circuit patterns. A mask is fabricated from the OPC circuit patterns, and may be used fabricate a semiconductor device.

Abstract: Provided is a method of fabricating a photo mask. The method includes preparing a model group including optical proximity correction (OPC) models and generating a preliminary mask layout using an integrated circuit (IC) layout. A contour image may be produced from the preliminary mask layout through a simulation using an optical model. Subsequently, the preliminary mask layout may be compared with the contour image and the comparison result may be analyzed to produce analysis data for providing criteria used in selecting an OPC model. An OPC model suitable for the preliminary mask layout may be selected from the model group based on the analysis data. An OPC process may be performed on the preliminary mask layout using the selected OPC model to generate a mask layout.

Abstract: Provided are a compensating mask, a multi-optical system using the compensating mask, and a method of compensating for a 3-dimensional (3-D) mask effect using the compensating mask. Methods of compensating for a 3-D mask effect using a compensating mask may include generating a first kernel corresponding to a normal mask used for forming a minute pattern, generating a second kernel corresponding to a compensating mask, mixing the first kernel corresponding to the normal mask with the second kernel corresponding to the compensating mask, and generating a multi-optical system kernel corresponding to mixing the first kernel and the second kernel.

Abstract: A pattern arrangement method of a semiconductor device is provided. In the pattern arrangement method, patterns are classified according to effective pitches and critical dimensions, and pattern dispersion is predicted according to the effective pitches and the critical dimensions by using a statistical analysis of process parameters. Two-dimensional coordinates of the effective pitches and the critical dimensions are constructed, and a dispersion map is made by arranging the predicted pattern dispersion on the corresponding coordinates. By arranging design patterns within a tolerance region of the dispersion map, the patterns satisfying the dispersion tolerance according to the significance of the layer and the design requirements can be arranged.

Abstract: Provided is a method of fabricating a photo mask. The method includes preparing a model group including optical proximity correction (OPC) models and generating a preliminary mask layout using an integrated circuit (IC) layout. A contour image may be produced from the preliminary mask layout through a simulation using an optical model. Subsequently, the preliminary mask layout may be compared with the contour image and the comparison result may be analyzed to produce analysis data for providing criteria used in selecting an OPC model. An OPC model suitable for the preliminary mask layout may be selected from the model group based on the analysis data. An OPC process may be performed on the preliminary mask layout using the selected OPC model to generate a mask layout.

Abstract: An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models.