Patents by Inventor Sung-Soon Kim

Sung-Soon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250185335
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Application
    Filed: February 4, 2025
    Publication date: June 5, 2025
    Applicant: SK hynix Inc.
    Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
  • Patent number: 12255237
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: March 18, 2025
    Assignee: SK hynix Inc.
    Inventors: Chang Soo Lee, Young Ho Yang, Sung Soon Kim, Hee Soo Kim, Hee Do Na, Min Sik Jang
  • Publication number: 20240349502
    Abstract: A memory device includes first and second material layers alternately stacked; a vertical hole passing through the first and second material layers; first insulating patterns protruding from a side surface of the first material layers exposed through the vertical hole; a blocking layer formed along a surface of the second material layers exposed between the first insulating patterns, the blocking layer comprising a plurality of concave portions, each of which is between the first insulating patterns; and charge trap patterns formed in the concave portions, wherein portions of the blocking layer exposed between the charge trap patterns, wherein a tunnel insulating layer, a channel layer, and a core pillar, are formed in an area that is substantially surrounded by the charge trap patterns.
    Type: Application
    Filed: September 20, 2023
    Publication date: October 17, 2024
    Applicant: SK hynix Inc.
    Inventors: Seok Min JEON, Min Ho LEE, Seong Man JEON, Tae Hong GWON, Sung Soon KIM, Ji Seong KIM, Ki Gab YEON, Sang Seob LEE
  • Patent number: 11955340
    Abstract: A method of manufacturing a semiconductor device includes forming a stack in which first material layers and second material layers are alternately stacked, forming a channel structure passing through the stack, forming openings by removing the first material layers, forming an amorphous blocking layer in the openings, and performing a first heat treatment process to supply deuterium through the openings and substitute hydrogen in the channel structure with the deuterium.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: April 9, 2024
    Assignee: SK hynix Inc.
    Inventors: Dae Hee Han, Sung Soon Kim
  • Publication number: 20240006495
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 4, 2024
    Applicant: SK hynix Inc.
    Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
  • Patent number: 11799003
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: October 24, 2023
    Assignee: SK hynix Inc.
    Inventors: Chang Soo Lee, Young Ho Yang, Sung Soon Kim, Hee Soo Kim, Hee Do Na, Min Sik Jang
  • Publication number: 20230317461
    Abstract: A method of manufacturing a semiconductor device includes forming a stack in which first material layers and second material layers are alternately stacked, forming a channel structure passing through the stack, forming openings by removing the first material layers, forming an amorphous blocking layer in the openings, and performing a first heat treatment process to supply deuterium through the openings and substitute hydrogen in the channel structure with the deuterium.
    Type: Application
    Filed: June 2, 2023
    Publication date: October 5, 2023
    Applicant: SK hynix Inc.
    Inventors: Dae Hee HAN, Sung Soon KIM
  • Patent number: 11710639
    Abstract: A method of manufacturing a semiconductor device includes forming a stack in which first material layers and second material layers are alternately stacked, forming a channel structure passing through the stack, forming openings by removing the first material layers, forming an amorphous blocking layer in the openings, and performing a first heat treatment process to supply deuterium through the openings and substitute hydrogen in the channel structure with the deuterium.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 25, 2023
    Assignee: SK hynix Inc.
    Inventors: Dae Hee Han, Sung Soon Kim
  • Publication number: 20230226529
    Abstract: There is provided a method of preparing a photoelectrochemical and electrochemical electrode catalyst, the method including preparing a metal oxide-based electrode, introducing a phosphate layer on a surface of the metal oxide-based electrode; and converting the phosphate layer into an oxyhydroxide layer by performing electrochemical activation on the phosphate layer. The efficiency of selective oxidation reaction of ammonia in wastewater may be improved.
    Type: Application
    Filed: September 23, 2022
    Publication date: July 20, 2023
    Inventors: Jung Kyu KIM, Jong Hyeok PARK, Won Tae HONG, Sung Soon KIM
  • Publication number: 20230113734
    Abstract: The present invention relates to a binding molecule that binds to SARS-coronavirus-2 (SARS-CoV-2). More particularly, the binding molecule of the present invention has strong ability to bind to a spike protein (S protein) on the surface of SARS-coronavirus-2 and high neutralizing activity against SARS-coronavirus-2 and is thus very useful in the diagnosis, prevention or treatment of SARS-coronavirus infection (COVID-19).
    Type: Application
    Filed: March 22, 2021
    Publication date: April 13, 2023
    Inventors: Cheol-Min KIM, Ji-Min SEO, Min-Soo KIM, Soo-Young LEE, Dong-Kyun RYU, Sung-Soon KIM, Joo-Yeon LEE, Kyung-Chang KIM, Jeong-Sun YANG, Han-Saem LEE, Hye-Min WOO, Jun-Won KIM
  • Publication number: 20220181455
    Abstract: A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a first source layer, a second source layer on the first source layer, a stack on the second source layer, a channel structure passing through the stack and the second source layer, and a common source line passing through the stack and the second source layer. The second source layer includes an air gap and a conductive layer surrounding the air gap.
    Type: Application
    Filed: April 15, 2021
    Publication date: June 9, 2022
    Applicant: SK hynix Inc.
    Inventors: Chang Soo LEE, Young Ho YANG, Sung Soon KIM, Hee Soo KIM, Hee Do NA, Min Sik JANG
  • Patent number: 11350040
    Abstract: When a three-dimensional image of a specific subject is acquired by means of an infrared camera and an external light (for example, external light such as sunlight at the time of outdoor photography) having a relatively large intensity exists, it is difficult to acquire the image. To this end, the present invention proposes an electronic device for reducing a current peak by adaptively changing optical power and an exposure time of an infrared camera according to the intensity of external light.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byeong-Hoon Park, Yong-Chan Keh, Sung-Soon Kim, Yong-Kwan Kim, Ki-Suk Sung, Dong-Hi Lee
  • Publication number: 20220123015
    Abstract: The technology relates to a semiconductor device and a method for manufacturing the semiconductor device. According to the technology, a method for manufacturing a semiconductor device may comprise forming a gapfill target structure on a semiconductor substrate, the gapfill target structure including a horizontal recess parallel with the semiconductor substrate and having a first surface and a vertical slit extending from the horizontal recess and having a second surface perpendicular to the semiconductor substrate, removing a native oxide from the first surface to form a pre-cleaned first surface, forming, in-situ, a first semiconductor material on the pre-cleaned first surface and forming a second semiconductor material on the first semiconductor material.
    Type: Application
    Filed: August 25, 2021
    Publication date: April 21, 2022
    Applicant: SK hynix Inc.
    Inventors: Hee Do NA, Sun Kak HWANG, Sung Soon KIM
  • Publication number: 20220059356
    Abstract: A method of manufacturing a semiconductor device includes forming a stack in which first material layers and second material layers are alternately stacked, forming a channel structure passing through the stack, forming openings by removing the first material layers, forming an amorphous blocking layer in the openings, and performing a first heat treatment process to supply deuterium through the openings and substitute hydrogen in the channel structure with the deuterium.
    Type: Application
    Filed: February 25, 2021
    Publication date: February 24, 2022
    Applicant: SK hynix Inc.
    Inventors: Dae Hee HAN, Sung Soon KIM
  • Patent number: 11094073
    Abstract: A method of calculating depth information for a three-dimensional (3D) image includes generating a pattern based on the value of at least one cell included in a two-dimensional (2D) image, projecting the pattern, capturing a reflected image of the pattern, and calculating depth information based on the reflected image of the pattern.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 17, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Andrii Volochniuk, Yong-Chan Keh, Jung-Kee Lee, Sung-Soon Kim, Sun-Kyung Kim, Andrii But, Andrii Sukhariev, Dmytro Vavdiyuk, Konstantin Morozov
  • Publication number: 20200280668
    Abstract: When a three-dimensional image of a specific subject is acquired by means of an infrared camera and an external light (for example, external light such as sunlight at the time of outdoor photography) having a relatively large intensity exists, it is difficult to acquire the image. To this end, the present invention proposes an electronic device for reducing a current peak by adaptively changing optical power and an exposure time of an infrared camera according to the intensity of external light.
    Type: Application
    Filed: September 19, 2018
    Publication date: September 3, 2020
    Inventors: Byeong-Hoon PARK, Yong-Chan KEH, Sung-Soon KIM, Yong-Kwan KIM, Ki-Suk SUNG, Dong-Hi LEE
  • Patent number: 10325924
    Abstract: A semiconductor device includes a stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Sung Ko, Sung Soon Kim, Wan Sup Shin
  • Publication number: 20190130590
    Abstract: A method of calculating depth information for a three-dimensional (3D) image includes generating a pattern based on the value of at least one cell included in a two-dimensional (2D) image, projecting the pattern, capturing a reflected image of the pattern, and calculating depth information based on the reflected image of the pattern.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 2, 2019
    Inventors: Andrii VOLOCHNIUK, Yong-Chan KEH, Jung-Kee LEE, Sung-Soon KIM, Sun-Kyung KIM, Andrii BUT, Andrii SUKHARIEV, Dmytro VAVDIYUK, Konstantin MOROZOV
  • Publication number: 20180301466
    Abstract: A semiconductor device includes a stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.
    Type: Application
    Filed: May 15, 2018
    Publication date: October 18, 2018
    Inventors: Min Sung KO, Sung Soon KIM, Wan Sup SHIN
  • Patent number: 9997532
    Abstract: A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min Sung Ko, Sung Soon Kim, Wan Sup Shin