Patents by Inventor Sunguk JANG
Sunguk JANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220085202Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: Youngdae Cho, Sunguk Jang, Sujin Jung, Jungtaek Kim, Sihyung Lee
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Patent number: 11251313Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.Type: GrantFiled: January 28, 2020Date of Patent: February 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Seung Mo Kang, Moon Seung Yang, Jongryeol Yoo, Sihyung Lee, Sunguk Jang, Eunhye Choi
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Publication number: 20220005958Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.Type: ApplicationFiled: September 21, 2021Publication date: January 6, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Sunguk JANG, Kihwan KIM, Sujin JUNG, Youngdae CHO
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Patent number: 11211456Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.Type: GrantFiled: January 24, 2020Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sujin Jung, Kihwan Kim, Sunguk Jang, Youngdae Cho
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Patent number: 11195954Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities.Type: GrantFiled: January 2, 2020Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Youngdae Cho, Sunguk Jang, Sujin Jung, Jungtaek Kim, Sihyung Lee
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Patent number: 11177346Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).Type: GrantFiled: October 29, 2019Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki Hwan Kim, Sunguk Jang, Pankwi Park, Sangmoon Lee, Sujin Jung
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Patent number: 11152517Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.Type: GrantFiled: January 6, 2020Date of Patent: October 19, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sunguk Jang, Kihwan Kim, Sujin Jung, Youngdae Cho
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Publication number: 20210143049Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin.Type: ApplicationFiled: December 30, 2020Publication date: May 13, 2021Inventors: Sunguk Jang, Seokhoon KIM, Seung Hun LEE, Yang XU, Jeongho YOO, Jongryeol YOO, Youngdae CHO
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Patent number: 10903108Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.Type: GrantFiled: January 12, 2018Date of Patent: January 26, 2021Inventors: Sunguk Jang, Seokhoon Kim, Seung Hun Lee, Yang Xu, Jeongho Yoo, Jongryeol Yoo, Youngdae Cho
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Publication number: 20200381546Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities.Type: ApplicationFiled: January 2, 2020Publication date: December 3, 2020Inventors: Youngdae Cho, Sunguk Jang, Sujin Jung, Jungtaek Kim, Sihyung Lee
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Publication number: 20200381563Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.Type: ApplicationFiled: January 6, 2020Publication date: December 3, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sunguk Jang, Kihwan Kim, Sujin Jung, Youngdae Cho
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Publication number: 20200381564Abstract: A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.Type: ApplicationFiled: January 28, 2020Publication date: December 3, 2020Inventors: Seung Mo KANG, Moon Seung YANG, Jongryeol YOO, Sihyung LEE, Sunguk JANG, Eunhye CHOI
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Publication number: 20200381562Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.Type: ApplicationFiled: December 16, 2019Publication date: December 3, 2020Inventors: Sujin Jung, Junbeom Park, Kihwan Kim, Sunguk Jang, Youngdae Cho
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Publication number: 20200365692Abstract: A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain; layer on the growth prevention pattern, the source/drain layer contacting the channels.Type: ApplicationFiled: January 24, 2020Publication date: November 19, 2020Inventors: Sujin Jung, Kihwan Kim, Sunguk Jang, Youngdae Cho
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Publication number: 20200219976Abstract: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).Type: ApplicationFiled: October 29, 2019Publication date: July 9, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Hwan KIM, Sunguk Jang, Pankwi Park, Sangmoon Lee, Sujin Jung
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Publication number: 20200075764Abstract: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.Type: ApplicationFiled: May 15, 2019Publication date: March 5, 2020Inventors: Sunguk JANG, Sujin JUNG, Jinyeong JOE, Jeongho YOO, Seung Hun LEE, Jongryeol YOO
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Publication number: 20190139811Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin.Type: ApplicationFiled: January 12, 2018Publication date: May 9, 2019Inventors: Sunguk Jang, Seokhoon KIM, Seung Hun LEE, Yang XU, Jeongho YOO, Jongryeol YOO, Youngdae CHO
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Patent number: 9627207Abstract: Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region.Type: GrantFiled: June 11, 2015Date of Patent: April 18, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sunguk Jang, Juyeon Kim, Hosung Son, Dongsuk Shin, Jeongmin Lee
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Publication number: 20160133728Abstract: Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region.Type: ApplicationFiled: June 11, 2015Publication date: May 12, 2016Inventors: Sunguk JANG, Juyeon KIM, Hosung SON, Dongsuk SHIN, Jeongmin LEE