Patents by Inventor Sung-won Lim

Sung-won Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11276761
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong-Soo Kim, Sung-Won Lim, Eun-Jeong Kim, Hyun-Jin Chang, Keun Heo, Jee-Hyun Kim
  • Patent number: 11103408
    Abstract: Provided are an obstetric and gynecologic diagnosis apparatus and an obstetric and gynecologic diagnosis method using the same. The obstetric and gynecologic diagnosis apparatus includes a chair unit on which an object is mounted, the chair unit including an upper body support, a seat, and a leg cradle sequentially arranged in one direction and connected to each other; a storage configured to store body information of the object; an input interface configured to input identification (ID) information of the object; a controller configured to generate a control signal for moving at least one of the upper body support, the seat, and the leg cradle according to first body information of the object identified by the input ID information; and a driver configured to generate a driving force for moving at least one of the upper body support, the seat, and the leg cradle according to the control signal.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG MEDISON CO., LTD.
    Inventors: Sung-won Lim, Ui Kim, Jun-pil Moon, Cheon-seop Shin, Kil-su Ha
  • Publication number: 20200152754
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Dong-Soo KIM, Sung-Won LIM, Eun-Jeong KIM, Hyun-Jin CHANG, Keun HEO, Jee-Hyun KIM
  • Patent number: 10553692
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong-Soo Kim, Sung-Won Lim, Eun-Jeong Kim, Hyun-Jin Chang, Keun Heo, Jee-Hyun Kim
  • Publication number: 20180085271
    Abstract: Provided are an obstetric and gynecologic diagnosis apparatus and an obstetric and gynecologic diagnosis method using the same. The obstetric and gynecologic diagnosis apparatus includes a chair unit on which an object is mounted, the chair unit including an upper body support, a seat, and a leg cradle sequentially arranged in one direction and connected to each other; a storage configured to store body information of the object; an input interface configured to input identification (ID) information of the object; a controller configured to generate a control signal for moving at least one of the upper body support, the seat, and the leg cradle according to first body information of the object identified by the input ID information; and a driver configured to generate a driving force for moving at least one of the upper body support, the seat, and the leg cradle according to the control signal.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 29, 2018
    Applicant: SAMSUNG MEDISON CO., LTD.
    Inventors: Sung-won LIM, Ui KIM, Jun-pil MOON, Cheon-seop SHIN, Kil-su HA
  • Publication number: 20170186844
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Application
    Filed: July 12, 2016
    Publication date: June 29, 2017
    Inventors: Dong-Soo KIM, Sung-Won LIM, Eun-Jeong KIM, Hyun-Jin CHANG, Keun HEO, Jee-Hyun KIM
  • Patent number: 9514980
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hyo-Seok Lee, Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Nam-Yeal Lee
  • Patent number: 9466603
    Abstract: A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Hyo-Seok Lee, Nam-Yeal Lee
  • Patent number: 9373681
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: June 21, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Publication number: 20160172304
    Abstract: This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures, The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalis of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.
    Type: Application
    Filed: February 12, 2016
    Publication date: June 16, 2016
    Inventors: Nam-Yeal LEE, Seung-Jin YEOM, Sung-Won LIM, Seung-Hee HONG, Hyo-Seok LEE, Dong-Seok KIM, Seung-Bum KIM, Se-Jin KIM
  • Patent number: 9337202
    Abstract: A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 10, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Publication number: 20160104764
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 14, 2016
    Inventors: Sung-Won LIM, Seung-Jin YEOM, Hyo-Seok LEE
  • Patent number: 9293362
    Abstract: This technology provides a semiconductor device and a method of fabricating the same, which may reduce parasitic capacitance between adjacent conductive structures. The method of fabricating a semiconductor device may include forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers over sidewalls of the contact holes, forming first plugs recessed into the respective contact holes, forming air gaps by removing the sacrificial spacers, forming capping structures capping the air gaps while exposing top surfaces of the first plugs, and forming second plugs over the first plugs.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Nam-Yeal Lee, Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Hyo-Seok Lee, Dong-Seok Kim, Seung-Bum Kim, Sei-Jin Kim
  • Publication number: 20160049409
    Abstract: A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.
    Type: Application
    Filed: October 27, 2015
    Publication date: February 18, 2016
    Inventors: Seung-Jin YEOM, Sung-Won LIM, Seung-Hee HONG, Hyo-Seok LEE, Nam-Yeal LEE
  • Patent number: 9245946
    Abstract: A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hyo-Seok Lee, Seung-Jin Yeom, Sung-Won Lim
  • Patent number: 9240442
    Abstract: A method for fabricating a capacitor of a semiconductor device includes forming a mold layer over a substrate, forming a plurality of preliminary openings by selectively etching the mold layer, forming a plurality of openings where each opening is formed to have a given linewidth by forming a sacrificial layer on sidewalls of the preliminary openings, and forming a plurality of storage nodes in the plurality of openings.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: January 19, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sung-Won Lim, Seung-Jin Yeom, Hyo-Seok Lee
  • Publication number: 20160005743
    Abstract: A semiconductor device includes a first conductive structure including a first conductive pattern that is formed over a substrate, a second conductive structure formed adjacent to a sidewall of the first conductive structure, and an insulation structure including an air gap that is formed between the first conductive structure and the second conductive structure, wherein the second conductive structure includes a second conductive pattern, an ohmic contact layer that is to formed over the second conductive pattern, and a third conductive pattern that is formed over the ohmic contact layer and is separated from the first conductive pattern through the air gap.
    Type: Application
    Filed: September 17, 2015
    Publication date: January 7, 2016
    Inventors: Sung-Won LIM, Seung-Jin YEOM, Hyo-Seok LEE
  • Publication number: 20150371891
    Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventors: Hyo-Seok LEE, Seung-Jin YEOM, Sung-Won LIM, Seung-Hee HONG, Nam-Yeal LEE
  • Patent number: 9202774
    Abstract: A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seung-Jin Yeom, Sung-Won Lim, Seung-Hee Hong, Hyo-Seok Lee, Nam-Yeal Lee
  • Patent number: D743539
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeon-Moo Chung, Sung-Won Lim, Cheon-Seop Shin