Abstract: A cryptographic device that will actively clear its memory even in the absence of external power when a security breach is detected is provided. The memory cell clusters of the cryptographic device are provided with an internal power source that provides sufficient energy for the memory cell clusters to perform a clearing operation. If the external power source for the memory is removed and a physical security breach is detected, the power from the internal power source will allow the memory cells to actively clear their contents, thereby rendering any attempt to obtain the contents of the memory cells fruitless.

Abstract: Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read only port. In another configuration, a physical partial dual-port non-volatile memory is provided having a secondary partial read only port.

Abstract: Systems and methods for providing memory access circuitry in application specific integrated circuits, and in certain configurations for recovering data from non-volatile memory registers in a partially disabled application specific integrated circuit as provided. In one configuration, a virtual partial dual-port non-volatile memory is provided having a secondary partial read only port. In another configuration, a physical partial dual-port non-volatile memory is provided having a secondary partial read only port.

Abstract: A cryptographic device that will actively clear its memory even in the absence of external power when a security breach is detected is provided. The memory cell clusters of the cryptographic device are provided with an internal power source that provides sufficient energy for the memory cell clusters to perform a clearing operation. If the external power source for the memory is removed and a physical security breach is detected, the power from the internal power source will allow the memory cells to actively clear their contents, thereby rendering any attempt to obtain the contents of the memory cells fruitless.

Abstract: A postage printing system includes a printer and a postage meter. The postage meter includes a controller for generating print information having a plurality of print data blocks necessary to print a postal indicia. The printer is located remotely from the postage meter and includes a controller and a printer for printing the postal indicia. The printer controller is in operative communication with the postage meter controller for receiving the plurality of print data blocks. The postage meter controller encrypts the plurality of print data blocks into a plurality of encrypted print data blocks, respectively, using a cypher block chaining encryption algorithm prior to transmitting the plurality of encrypted print data blocks to the printer controller where they are decrypted by the printer controller. Check numbers for each print data block and validation of the check numbers may be employed at the printer controller.

Abstract: A mail handling system includes a printhead for printing a postage indicium on a mailpiece; a transport mechanism that moves the mailpiece past the printhead during printing of the postage indicium; a postage meter including means for accounting for a value of postage associated with the postage indicium; an image generator in operative communication with the postage meter, the image generator producing a synchronous image data stream for use by the printhead in printing the postage indicium; a buffer which receives and stores the synchronous image data stream from the image generator; apparatus for switching the image generator between an ON status whereby the image generator produces the synchronous image data stream and an OFF status whereby the image generator does not produce the synchronous image data stream based upon the occurrence of a predetermined condition; structure for transferring the stored synchronous image data stream to the printhead in an asynchronous manner; and wherein the switching appa

Abstract: An electronic postage meter control system having a printer for printing mixed graphic and alphanumeric information. The control system includes a programmable microprocessor in bus communication with the printer for controlling the printer and with a plurality of memory units for accounting for postage printed by the printer. The memory units include at least a first memory unit having a write access time shorter than the write access time of a second one of said memory unit, a program memory in bus communication with the programmable microprocessor having an operating program stored therein. The programmable microprocessor is able to access the operating program, an integrated circuit, the program memory, and said first and second units. The integrated circuit has an address decoding module for generating one of a plurality control signals in a unique combination in response to a respective request by the programmable microprocessor.

Abstract: The memory access limiting circuit detects when two or more of memory units associated with a microprocessor control system have been accessed enabled concurrently representing an error condition. The memory access limiting circuit is part of an integrated circuit. The integrated circuit also includes an address decoding for receiving the unique address signal and causing a write enable signal to be generated for the memory units and one of a plurality chip select signals to be generated for a respective one of the memory units. The monitoring circuit monitors the pin levels of the integrated circuit assigned for enabling the respective memory unit. The monitoring circuit generates a first output signal when a respective one of the memory unit chip select signals has been enabled and a second output signal when a plurality of chip select signals have been enabled. The second output signal is directed to the microprocessor for corrective action.

Abstract: The memory security circuit detects when a memory unit has been accessed independently of an address instruction of a programmable microprocessor. The microprocessor is programmed to provide a unique address signal for write enabling a discrete memory unit. The memory unit has a write enable pin and chip select pin which when enabled in combination permits writing into the memory unit. The address decoder receives the unique address instruction and causes a write enable signal and a chip select signal to be generated for that memory unit. The write enable signal and chip select signal are to be received, respectively, by the write enable pin and the chip select pin of the memory unit. The memory security circuit monitors the write enable pin and the chip select pin of the memory unit and generates a first output signal when the memory unit has been properly addressed.

Abstract: The printer control module is programmed to output control signals to the printer driver characterized by the data written in the control registers. The control system for a printing apparatus includes a printer unit responsive to a printer driver unit. The printer driver unit is responsive to the control system. The control system has a programmable printer control module in communication with the printer driver unit and a programmable microcomputer in bus communication with the printer control module. The microcomputer has a non-volatile memory unit for storing the data. The printer driver unit is responsive to control signals from the printer control module for driving the printer unit. The printer control module includes a buffer for holding printer data and the registers of the control module, including a control register, a shift register and a strobe width register.

Abstract: A micro control system includes a programmable microcontroller which is in bus communication with memory units and a operating power supply for providing operating power to said microcontroller. A communication module is part of the micro control system and is in communication with the data bus of the micro control system for receiving and transmitting data messages to an external device, and for encoding said transmitted data messages to conform to a serial communication protocol and decoding said received data messages. The microcontroller is programmed to generated a first control signal or a second control signal. An input-output interface is included as part of the micro control system and includes a number of switching units responsive to the first control signal of the microcontroller to place the respective switching units in a first mode of operation for providing communication between said communication module and a connector.

Abstract: The data encryption system includes a first stage and a second stage data encryption engine in combination with a micro control system. The data encryption system is responsive to control signals from the micro control system. The first stage is comprised of an 8-bit bus input and output from the first stage to the second stage data encryption engine of 64-bits. The input bus of the first stage is gated to a plurality of 8-bit registers through a plurality of AND gates having a respective one of the AND gate inputs in communication with the 8-bit bus and output from the respective AND gate directed to a respective input of the respective 8-bit registers for selectively gating data from the 8-bit bus to respective ones of the 8-bit registers.

Abstract: An apparatus for producing an image in a mail handling machine includes a printing device and a non-volatile memory having fixed and variable image data elements stored therein, a first portion of the fixed image data elements being stored in a compressed manner and a second portion of the fixed image data elements being stored in a bit map form.

Abstract: The control system controls the operation of a charge coupled device. The operation of the charge coupled device is responsive to a shift clock signal of a given frequency and a shift enable signal. The control system includes a timer for generating one of a number of shift clock signals. Each of the shift clock signals has a different frequency. A programmable register stores a plurality of control bits which may be programmed into the program memory of the control system. A multiplex switching is used for selecting one of the shift clock signals in response to the state of the control bits and directing the selected shift clock signal to the charge coupled device. An address decoder in response to addressing by the microprocessor, generates the shift enable signal which signal is directed to the charge coupled device concurrently with the presence of the selected shift clock signal.

Abstract: The method for preventing monitoring of postage indicia data which is sent from a postage metering vault to a remotely located digital printer over a communication link between the meter vault and the digital printer. The meter is provided with an encryption engine for encrypting postage indicia data utilizing a encryption key. The digital printer includes a decryption engine for decrypting postage data received from said meter utilizing the same encryption key and then prints a postage indicia pursuant to the decrypted postage indicia data. The postage meter also includes a key manager for generating new encryption key pursuant to a token which is either randomly generated or generated pursuant to an algorithm by a similar encryption key manager located in the digital printer which token is also used to generate the decryption key for the decryption engine. As a result, the encryption keys are the same.

Abstract: The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to a control circuit. The control circuit is comprised of a programmable microprocessor in bus communication with an accounting medium having memory units for accounting for the postage printed by the printing unit responsive to the programming of the microprocessor. An integrated circuit includes an address decoding module for generating a unique combination of ASIC control signals in response to a respective address placed on the bus by the microprocessor. A timer register is responsive to ones of the control signals from the address decoding module to enable writing of the timer data into the timer registers by the microprocessor. The timer unit is responsive to the timer data for generating one of a plurality of timing signals in accordance with timer data. Also included are a plurality of non-volatile memory units.

Abstract: The micro-controller system is comprised of a programmable microprocessor, a plurality of memory units having a plurality of addressable memory registers. The memory units are in bus communication with the programmable processor and an application specific integrated circuit. The application specific integrated circuit includes a circuit for dividing the memory units into a plurality of addressable regions in response to programming of the programmable microprocessor. The microprocessor is programmed such that the initial address for each of the regions is assigned by the most significant address bits, and the uppermost address for the region being programmably defined by an uppermost address for the respective region. The circuit includes a plurality of addressable registers.

Abstract: The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to control circuit. The control circuit is comprised of a programmable microprocessor in bus communication with an accounting means having memory units for accounting for the postage printed by the printing unit responsive to the programming of the microprocessor. An integrated circuit includes an address decoding module means for generating a unique combination of ASIC control signals in response to a respective address placed on the bus by the microprocessor. A timer register is responsive to ones of the control signals from the address decoding module to enable writing of the timer data into the timer registers by the microprocessor. The timer unit is responsive to the timer data for generating one of a plurality of timing signal in accordance with timer data. The data also includes motor data.

Abstract: A programmable timer circuit which is integrated into an application specific integrated circuit includes a programmable timer counter. The programmable timer counter receives count data which is written to registers of the integrated circuit and is caused to initiate a count until that count is reached in response to clock signal. A programmable microprocessor is provided for controlling the programmable timer circuit and reading count data and mode data from non-volatile memory units in response to the microprocessor's programming and writing the count data and mode data into the registers of the application specific integrated circuit. In response to the mode data the programmable timer circuit assumes either a one shot mode or a continuos mode when the programmable timer.

Abstract: A programmable timer circuit is comprised of a programmable timer counter for receiving a count and for counting to the count. A clock signal for driving the timer counter which timer counter generates a signal representative of the count. A microprocessor generates count data in response to programming of the microprocessor. Timer data register receive the count from microprocessor. A first gate is provided having an enabled mode and an non-enabled mode for enabling loading of the timer data from the timer data register to the timer counter input only in the enabled mode. A monitoring circuit is provided for monitoring the timer count and enabling the gate mean to the enabled mode only when the timer has time-out.