Abstract: A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.

Abstract: Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory system includes a host, a first memory module communicating with the host through a first interface and a second memory module communicating with the host through a second interface. The host comprises a prefetch table storage and a map manager. The prefetch table storage may store a prefetch table indicating candidate data to be prefetched to the first memory module among data stored in the second memory module. The map manager may prefetch target data from the second memory module to the first memory module according to whether the target data is included in the candidate data when the target data requested by the host is cache-missed in the first memory module and is cache-hit in the second memory module.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory module communicating with a host through a compute express link (CXL) interface includes a non-volatile memory device, a volatile memory device and a memory controller. The non-volatile memory device may store data. The memory controller may select candidate data to be prefetched among the data based on access pattern information of the host for the data and a plurality of algorithms, and prefetch target data among the candidate data to the volatile memory device.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory system includes a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface and having a tier lower than that of the first memory module. The first memory module comprises a memory device and a memory controller. The memory device may store cache data. The memory controller may store access pattern information of the host for the memory device, select candidate data to be evicted among the cache data based on the access pattern information of the host and a plurality of algorithms, and evict target data among the candidate data.

Abstract: Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.

Abstract: The disclosed technology relates to an electronic device with a memory module. In some implementations, a memory module may include a memory device and a memory controller. The memory device may store data. The memory controller may communicate with an external device through a first interface and the memory device through a second interface, and set a type of the second interface as a parallel interface or a serial interface according to a ratio between a first request and a second request received from the external device.

Abstract: A memory system includes: a main memory device configured to include a plurality of row lines; a cache memory device configured to include a plurality of cache lines for caching data stored in the row lines, each cache line including cache data, a row hammer state value for storing an access number of a corresponding row line, and an access selection bit set according to the row hammer state value; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device, which is selected according to the access selection bit of a cache-hit cache line, in response to a request from a host.

Abstract: Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.

Abstract: A memory system includes: a main memory device configured to include a plurality of row lines; a cache memory device configured to include a plurality of cache lines for caching data stored in the row lines, each cache line including cache data, a row hammer state value for storing an access number of a corresponding row line, and an access selection bit set according to the row hammer state value; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device, which is selected according to the access selection bit of a cache-hit cache line, in response to a request from a host.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory module that communicates with a host through a compute express link (CXL) interface may include a memory device and a memory controller. The memory device may store data. The memory controller may store access pattern information of the host for data, select candidate data to be prefetched from among the data based on the access pattern information of the host and a plurality of algorithms, and prefetch target data among the candidate data.

Abstract: A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.

Abstract: A method of fabricating a semiconductor device includes performing pre-halo ion implantation on a semiconductor substrate, forming a first epitaxial layer over the entire upper surface of the semiconductor substrate, forming a second epitaxial layer over the entire surface of the first epitaxial layer, and forming a transistor at an active region of the second epitaxial layer. The first epitaxial layer prevents the ions implanted in the semiconductor substrate in the pre-halo implantation process from diffused into the second epitaxial layer under the effects of a process used to form the transistor.

Abstract: A semiconductor device includes a substrate, a first region and a second region. Each of the first region and second region includes a trench, an epitaxial layer including a source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the source/drain and the second part extending from the top surface of the substrate to a bottom surface of the source/drain in the trench. The cross-sectional shape of the first part of the source/drain of the first region is the same as the cross-sectional shape of the first part of the source/drain of the second region. The cross-sectional shape of the second past of the source/drain of the find region is different from the cross-sectional shape of the second part of the source/drain of the second region.

Abstract: A method of fabricating a semiconductor device includes performing pre-halo ion implantation on a semiconductor substrate, forming a first epitaxial layer over the entire upper surface of the semiconductor substrate, forming a second epitaxial layer over the entire surface of the first epitaxial layer, and forming a transistor at an active region of the second epitaxial layer. The first epitaxial layer prevents the ions implanted in the semiconductor substrate in the pre-halo implantation process from diffused into the second epitaxial layer under the effects of a process used to form the transistor.

Abstract: A semiconductor device includes a substrate, a first region and a second region. Each of the first region and second region includes a trench, an epitaxial layer including a source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the source/drain and the second part extending from the top surface of the substrate to a bottom surface of the source/drain in the trench. The cross-sectional shape of the first part of the source/drain of the first region is the same as the cross-sectional shape of the first part of the source/drain of the second region. The cross-sectional shape of the second part of the source/drain of the first region is different from the cross-sectional shape of the second part of the source/drain of the second region.

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract: A method of fabricating a vertical NAND semiconductor device can include changing a phase of a first preliminary semiconductor layer in an opening from solid to liquid to form a first single crystalline semiconductor layer in the opening and then forming a second preliminary semiconductor layer on the first single crystalline semiconductor layer. The phase of the second preliminary semiconductor layer is changed from solid to liquid to form a second single crystalline semiconductor layer that combines with the first single crystalline semiconductor layers to form a single crystalline semiconductor layer in the opening.

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract: A metal-based photonic device package module that is capable of greatly improving heat releasing efficiency and implementing a thin package is provided. The metal-based photonic device package module includes a metal substrate that is formed the shape of a plate, a metal oxide layer that is formed on the metal substrate to have a mounting cavity, a photonic device that is mounted in the mounting cavity of the metal oxide layer, and a reflecting plane that is formed at an inner surface of the mounting cavity of the metal oxide layer.