Patents by Inventor Sunhom (Steve) Paak

Sunhom (Steve) Paak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11876019
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Publication number: 20220301939
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 22, 2022
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Publication number: 20220068718
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 3, 2022
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Patent number: 11201086
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 14, 2021
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Publication number: 20210249311
    Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. Apart that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.
    Type: Application
    Filed: April 29, 2021
    Publication date: August 12, 2021
    Inventors: Sunhom Steve Paak, Xiaolong Ma, Yanxiang Liu, Daxiang Wang, Zanfeng Chen, Yu Xia, Huabin Chen, Yongjie Zhou
  • Publication number: 20200227321
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Patent number: 10643898
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Patent number: 10497608
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HeonJong Shin, Sungmin Kim, Byungseo Kim, Sunhom Steve Paak, Hyunjun Bae
  • Patent number: 10403754
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Publication number: 20190148216
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: HeonJong SHIN, Sungmin KIM, Byungseo KIM, Sunhom Steve PAAK, Hyunju BAE
  • Patent number: 10204821
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HeonJong Shin, Sungmin Kim, Byungseo Kim, Sunhom Steve Paak, Hyunjun Bae
  • Patent number: 10199499
    Abstract: A semiconductor device includes first through fourth active fins, which extend alongside one another in a first direction; and a field insulating film that covers lower portions of the first through fourth active fins, the first and second active fins protrude from the field insulating film at a first height, the third active fin protrudes from the field insulating film at a second height different from the first height, and an interval between the first and second active fins is different from an interval between the third and fourth active fins.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Dong-Ho Cha, Sunhom Steve Paak
  • Publication number: 20180254341
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Application
    Filed: May 3, 2018
    Publication date: September 6, 2018
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Patent number: 10043873
    Abstract: Provided is a semiconductor device with a field effect transistor. The semiconductor device includes a substrate, an active pattern on the substrate, a gate electrode crossing the active pattern and a capping structure on the gate electrode. The capping structure includes first and second capping patterns that are sequentially stacked on the gate electrode. The second capping pattern completely covers a top surface of the first capping pattern, and a dielectric constant of the second capping pattern is greater than that of the first capping pattern.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Hwan Yeo, Seonguk Park, Seungjae Lee, Doyoung Choi, Sunhom Steve Paak, Tae Eung Yoon, Dongho Cha, Ruiyi Chen
  • Publication number: 20180190543
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Application
    Filed: February 23, 2018
    Publication date: July 5, 2018
    Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
  • Patent number: 9991387
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Sunhom Steve Paak, Yeon-Ho Park, Dong-Ho Cha
  • Patent number: 9978746
    Abstract: Provided is a semiconductor device with a field effect transistor. The semiconductor device may include a substrate including an active pattern, a separation structure crossing the active pattern and dividing the active pattern into first and second region. The separation structure may include a first insulating pattern that fills a recess region between the first and second regions. The first insulating pattern may have a concave top surface.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Hwan Yeo, KeunHee Bai, Seungseok Ha, Eunsil Park, Sunhom Steve Paak, Heonjong Shin, Dongho Cha
  • Patent number: 9905468
    Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Min Kim, Sunhom Steve Paak, Heon-Jong Shin, Dong-Ho Cha
  • Patent number: 9755049
    Abstract: Methods for fabricating semiconductor devices are provided including sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate, forming first mandrels on the first sacrificial layer by etching the second sacrificial layer, forming first spacers on side walls of the first mandrels, forming a photoresist pattern disposed outside a region from which the first mandrels have been removed, forming second and third mandrels by etching the first sacrificial layer using the first spacers and the photoresist pattern as respective etching masks, forming second and third spacers on side walls of the second and third mandrels, forming first and second active patterns respectively having first and second pitches by etching the hardmask layer and at least a portion of the substrate, and forming a device isolation layer so that upper portions of the first and second active patterns protrude therefrom.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunhom Steve Paak, Sung Min Kim
  • Patent number: 9679815
    Abstract: A semiconductor device fabrication method includes sequentially forming a hard mask layer and a sacrificial layer on a substrate, forming an upper mandrel which includes first to third upper sub-mandrels on the sacrificial layer, the first to third upper sub-mandrels extending in a first direction and being spaced apart from each other in a second direction, a width of the first upper sub-mandrel being smaller than widths of the second and third upper sub-mandrels, forming first spacers on sidewalls of each of the upper sub-mandrels, removing the upper mandrel, etching the sacrificial layer using the first spacers as etching masks to form a lower mandrel that includes a plurality of sub-mandrels, forming second spacers on sidewalls of the lower sub-mandrels, removing the lower mandrel, patterning the hard mask layer and the substrate using the second spacers as etching masks to form first to tenth fins which extend alongside each other in the first direction and are spaced apart from each other in the second
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 13, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Lee, Sunhom Steve Paak