Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.

Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.

Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.

Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.

Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.

Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.

Abstract: Techniques for implementing a secure graphics architecture are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module, and the graphics management module may be operative to receive graphics information from the processor circuit, generate graphics processing information based on the graphics information, and send the graphics processing information to a graphics processor circuit arranged to generate graphics display information based on the graphics processing information. In this manner, security threats such as screen capture attacks and/or theft of content protected media streams may be reduced. Other embodiments may be described and claimed.

Abstract: A device includes an enclosure and logic. The enclosure includes a plurality of capacitive touch sensor arrays disposed at least on two of a top side, a bottom side, a left side, a right side, a front side, and a back side of the device. The enclosure also includes a first display on the front side of the device. The logic receives touch interaction information from the plurality of capacitive touch sensor arrays and initiates an action based at least in part on the touch interaction information.

Abstract: Techniques for implementing a secure graphics architecture are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module, and the graphics management module may be operative to receive graphics information from the processor circuit, generate graphics processing information based on the graphics information, and send the graphics processing information to a graphics processor circuit arranged to generate graphics display information based on the graphics processing information. In this manner, security threats such as screen capture attacks and/or theft of content protected media streams may be reduced. Other embodiments may be described and claimed.

Abstract: A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet based interconnect. The graphics memory switch generates a physical system memory address and delivers the physical address to a root complex. The physical system memory address is delivered to the root complex via a point-to-point, packet based interconnect.

Abstract: A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet based interconnect. The graphics memory switch generates a physical system memory address and delivers the physical address to a root complex. The physical system memory address is delivered to the root complex via a point-to-point, packet based interconnect.

Abstract: A graphics device delivers a graphics address to a graphics memory switch that includes a graphics random access memory translator and a graphics memory page table. The graphics memory address is delivered to the graphics memory switch via a point-to-point, packet based interconnect. The graphics memory switch generates a physical system memory address and delivers the physical address to a root complex. The physical system memory address is delivered to the root complex via a point-to-point, packet based interconnect.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.