Patents by Inventor Sunil A. Patel

Sunil A. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150264536
    Abstract: A method of determining a present location of a mobile device within a structure includes: obtaining a prior location of the mobile device, the prior location being on a first floor of the structure; and in response to the prior location being indicative of the present location being remote from a floor transition, using a first set of access points to determine the present location, the first set of access points disposed only on the first floor; or in response to the prior location being indicative of the present location being proximate to the floor transition, using a second set of access points to determine the present location of the mobile device, the second set of access points comprising one or more access points disposed on the first floor and one or more access points disposed on the second floor, the second floor being separate from the first floor.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Milind H. PATIL, Sunil A. PATEL, Gaurav LAMBA
  • Patent number: 6618938
    Abstract: The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: September 16, 2003
    Assignee: LSI Logic Corporation
    Inventors: Maniam Alagaratnam, Kishor V. Desai, Sunil A. Patel
  • Patent number: 6466038
    Abstract: A method for measuring electromigration includes the steps of measuring a corresponding voltage increase across an interconnect as a function of time for a plurality of nonzero heating rates and calculating an interconnect integrity from the voltage increase.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: October 15, 2002
    Assignee: LSI Logic Corporation
    Inventors: Senol Pekin, Sunil A. Patel
  • Patent number: 6433565
    Abstract: A test fixture for a ball grid array package is disclosed that includes a test ball grid array package having a plurality of coarse pitch contacts formed on a coarse pitch surface of the test ball grid array package and a plurality of wafer bumps formed on a fine pitch surface of the test ball grid array package and an interposer coupled to the plurality of wafer bumps formed on the fine pitch surface of the test ball grid array package for coupling to a plurality of wafer bumps formed on a fine pitch surface of a subject ball grid array package.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: August 13, 2002
    Assignee: LSI Logic Corporation
    Inventors: Kishor V. Desai, Maniam Alagaratnam, Sunil A. Patel
  • Patent number: 6335491
    Abstract: The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: January 1, 2002
    Assignee: LSI Logic Corporation
    Inventors: Maniam Alagaratnam, Kishor V. Desai, Sunil A. Patel
  • Patent number: 6306751
    Abstract: Provided is an apparatus and method for modifying the manufacture of chip carrier bond pads to increase the quality and reliability of semiconductor packages and ball joints in particular. This is accomplished by minimizing the corrosion of the barrier metal layer on the functional bond pads during gold deposition with the use of sacrificial pads electrically connected with the functional bond pads. According to one embodiment of the invention, a semiconductor package has copper conductive pads on a substrate that are exposed through a dielectric. Both functional and sacrificial (nonfunctional) copper conductive pads are provided. A barrier metal layer composed of nickel is electrolessly plated onto these conductive pads, and a bond metal layer of gold is deposited onto the nickel using electroless, generally immersion, gold plating.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: October 23, 2001
    Assignee: LSI Logic Corporation
    Inventors: Sunil A. Patel, Chok J. Chia, Kishor V. Desai
  • Patent number: 6166434
    Abstract: Provided is a die clip for use in semiconductor flip chip packaging as a replacement for the conventional combination of a heat spreader and stiffener, a packaging method using the die clip, and a semiconductor package incorporating the die clip. In a preferred embodiment, the die clip is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The die clip closely engages the die while leaving some space open around the perimeter to provide access to the die. An underfill material may then be dispensed into the gap between the die and the substrate through an opening in the die clip. The underfill material is then cured, the die clip providing a heat sink and keeping the die and substrate flat and immobile during and after the curing process. A BGA process may then be used to apply solder balls to the underside of the substrate for subsequent bonding of the package to a circuit board for use.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: December 26, 2000
    Assignee: LSI Logic Corporation
    Inventors: Kishor V. Desai, Sunil A. Patel, John P. McCormick
  • Patent number: 6020221
    Abstract: The subject method comprises providing a semiconductor package and a semiconductor package substrate having respective first and second major sides. A stiffener member, which is attachable to the semiconductor package substrate, is employed for purposes of minimizing package warpage. The stiffener member is attached to the semiconductor package substrate to provide the requisite support for the semiconductor package substrate during the assembly process and thereby counteract the sources of the package warpage problem. A protective outer layer can be optionally added to the subject system.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: February 1, 2000
    Assignee: LSI Logic Corporation
    Inventors: Sengsooi Lim, Ramaswamy Ranganathan, Sunil A. Patel
  • Patent number: 6002171
    Abstract: Provided is a multi-piece integrated heat spreader/stiffener assembly which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener assembly has two pieces, both composed of a high modulus, high thermal conductivity material shaped to attach to each other and a die on the surface of a packaging substrate. A first piece of this assembly is bonded to the substrate surface adjacent to an electrically connected die and to the top surface of the die prior to the dispensation and curing of underfill material which provides the mechanical connection between the die and the substrate. With the first piece of the assembly in place, access may still be had to at least one edge of the die to dispense and cure the underfill epoxy.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: December 14, 1999
    Assignee: LSI Logic Corporation
    Inventors: Kishor V. Desai, Sunil A. Patel, John P. McCormick
  • Patent number: 5998242
    Abstract: A semiconductor chip fabrication assembly and method including a semiconductor package having a packaging substrate and a semiconductor die. An active circuit surface of the semiconductor die is positioned adjacent to a contact surface of the packaging substrate such that a substantially thin gap is formed therebetween. A semi-rigid shroud device is provided which defines a vacuum chamber configured to extend around the gap to hermetically seal the gap within the vacuum chamber. A dispensing device is provided having an outlet end positioned proximate the gap in the vacuum chamber which is adapted to vacuum flow the bonding material between the electrical contacts in the gap, and between the active circuit surface and the contact surface. The absence of air and any other gases forms a substantially voidless underfill layer of bonding material in the gap.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: December 7, 1999
    Assignee: LSI Logic Corporation
    Inventors: Galen C. Kirkpatrick, Manickam Thavarajah, Sunil A. Patel, Stephen A. Murphy
  • Patent number: 5909057
    Abstract: Provided is a single-piece integrated heat spreader/stiffener which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The heat spreader/stiffener is equipped with a plurality of apertures to provide access to the top surface of the die for adhesive to bond the heat spreader/stiffener to the die, and to its perimeter to provide access for dispensation of underfill material between the die and the substrate. Once the adhesive and underfill materials are in place, the adhesive and underfill resins are cured by heating.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: June 1, 1999
    Assignee: LSI Logic Corporation
    Inventors: John P. McCormick, Sunil A. Patel