Abstract: Flexible routing of gate arrays increases routing efficiency, provides for the routing of functional blocks with other gates in the gate array, and provides structures for flexible power routing, particularly of gate arrays having functional blocks. In particular, a gate-array-implemented integrated circuit is designed using a computer by representing in computer memory a gate array base, placing gate array cells on the gate array base in placement rows each having a uniform height and separated by routing channels in which no gate array cells are placed, and routing in the routing channel connections between placement rows according to a netlist, during routing increasing the size of a routing channel if required and decreasing the size of a routing channel if possible by changing the placement of at least one placement row by an amount less than half the height of the placement row. Routing channel size is therefore flexibly adjusted "on-the-fly" during routing, increasing routing efficiency.