Abstract: High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.

Abstract: An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a P-well of a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.

Abstract: A method of providing oxide layers at the surface of the semiconductor substrate suitable for use with the formation of programmable logic devices. The method comprises the steps of: depositing a layer of nitride on the surface of the semiconductor substrate; etching a first and second portions of the nitride layer; forming a first and second regions of a first oxide layer on the substrate in the first and second etched portions of the nitride layer; etching a the first region of the oxide; forming a second oxide layer on the substrate having a first portion in the first etched portion of the nitride and a second portion overlying the first portion of the second region of the first oxide layer; removing the nitride layer; and forming a third layer of oxide having a first portion on the surface of the substrate, a second and third portions on the first and second portions of the second oxide layer.

Abstract: A semiconductor device formed in a semiconductor substrate with a low hydrogen content barrier layer formed over the semiconductor device. The barrier layer is implanted with phosphorus ions. The semiconductor device may have a hydrogen getter layer formed under the barrier layer. The barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between 1000 and 2000 Angstroms and is a PSG, BPSG, PTEOS deposited oxide film, or BPTEOS deposited oxide film. Interconnects are made by a tungsten damascene process.

Abstract: A method for forming an oxide on the surface of a semiconductor substrate. The method includes the steps of: placing the semiconductor substrate in an atmosphere containing an atmosphere of an oxide growth inhibiting compound; applying laser energy to at least a first portion of the substrate; and forming the oxide on the surface of the substrate by heating the substrate. In a further aspect of the invention, the method comprises applying laser energy through a patterned, reflective reticle. Alternatively, prior to the step of placing, a reflective mask layer may be applied to the surface of the semiconductor substrate. In addition, the invention comprises an EEPROM memory cell having a program junction region in a semiconductor substrate. The cell comprises at least a first program junction provided in the silicon substrate and a floating gate having a portion positioned over the program junction.

Abstract: A shallow trench isolation structure and a method for forming the same for use with non-volatile memory devices is provided so as to maintain sufficient data retention thereof. An epitaxial layer is formed on a top surface of a semiconductor substrate. A barrier oxide layer is formed on a top surface of the epitaxial layer. A nitride layer is deposited on a top surface of the barrier oxide layer. Trenches are formed through the epitaxial layer and the barrier oxide layer to a depth greater than 4000 .ANG. below the surface of the epitaxial layer so as to create isolation regions in order to electrically isolate active regions in the epitaxial layer. A liner oxide is formed on sidewalls and bottom of the trenches to a thickness between 750 .ANG. to 1500 .ANG.. As a result, leakage current in the sidewalls are prevented due to less thinning of the liner oxide layer by subsequent fabrication process steps.

Abstract: A process for forming CMOS transistors on a semiconductor substrate, wherein the plurality of transistors includes high-voltage N-channel and high-voltage P-channel transistors, and low-voltage N-channel and low-voltage P-channel transistors, wherein a tunnel oxide of a first thickness is required and a gate oxide of a second thickness is required is provided.

Abstract: The present antifuse includes a base having a first electrode thereon which defines a top surface and a side surface. Antifuse material is disposed on the first electrode on at least a portion of the top surface and at least a portion of the side surface, with a second electrode on the antifuse material. Due to this configuration, defect problems in etching oxide as part of the antifuse structure are avoided, and meanwhile capacitance of the device is very low.