Abstract: A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.