Abstract: A storage switch in accordance with an embodiment of the invention is a highly scalable switch that allows the creation of a SAN that is easy to deploy and that can be centrally managed. Moreover, such a storage switch also allows the deployment of a global infrastructure, allowing the resources of the SAN, such as storage devices, to essentially be positioned anywhere on the globe. Further, such a storage switch allows a multi-protocol SAN, e.g., one that includes both iSCSI or Fibre Channel, and processes data packets at “wire speed.” To further enable wire-speed processing, a switch in accordance with the invention has “intelligence” distributed to each of its linecards, through which it classifies packets into data and control packets, it performs virtualization functions, and it performs protocol translation functions. A switch in accordance with the invention further performs serverless storage services such as mirroring, snapshot, and replication.

Abstract: A storage switch in accordance with an embodiment of the invention is a highly scalable switch that allows the creation of a SAN that is easy to deploy and that can be centrally managed. Moreover, such a storage switch also allows the deployment of a global infrastructure, allowing the resources of the SAN, such as storage devices, to essentially be positioned anywhere on the globe. Further, such a storage switch allows a multi-protocol SAN, e.g., one that includes both iSCSI or Fibre Channel, and processes data packets at “wire speed.” To further enable wire-speed processing, a switch in accordance with the invention has “intelligence” distributed to each of its linecards, through which it classifies packets into data and control packets, it performs virtualization functions, and it performs protocol translation functions. A switch in accordance with the invention further performs serverless storage services such as mirroring, snapshot, and replication.

Abstract: A computer system includes a bus interface with a plurality of data buffers. Each data buffer is clocked by an individual clock signal. To reduce the power consumption of the bus interface unit, the clock signals of the data buffers that are inactive are disabled during the period of inactivity. The bus interface unit includes a clock control unit that monitors a data bus coupled to the bus interface to determine when a bus cycle begins and the type of bus cycle. The clock control unit additionally monitors memory and CPU buffer signals that indicate which, if any, buffers are being accessed by the memory or CPU. From this information, the clock control unit determines which buffers are active and inactive, and outputs control signals to a clock unit to disable the clock signals associated with inactive buffers.