Abstract: Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Abstract: Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Abstract: Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Abstract: A method for limiting power consumption in a multiprocessor chip is provided. In this method, a read or write request is received by the memory controller, which controls a memory that is external to the multiprocessor chip. The memory controller includes a bank counter that keeps track of the number of read or write requests received by the memory controller. At every clock cycle, the bank counter value is compared with a threshold value to determine whether the counter value is equal to the threshold value. If the bank counter value is determined to be equal to the threshold value, then any subsequent incoming read or write requests are blocked. The bank counter value is incremented each time a read or write request is sent to the memory.

Abstract: A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with writing data into a storage element asynchronously according to a first clock domain. Next, the data is read from the storage element synchronously according to a second clock domain. A microprocessor and a system wherein data is read over a bi-directional bus are included.

Abstract: A memory interface comprising a first data input for receiving a data line to be stored in memory, a bad chip register containing a bad chip value for identifying a bad memory chip of a memory device to be used with the memory interface, and a write shift logic circuit receiving the data line from the first data input. The data line contains a plurality of data bits and a plurality of check bits, the check bits being logically appended to one end of the data bits. The write shift logic, in response to the bad chip value, causes a portion of the data line to be shifted toward the one end of the bad memory chip.

Abstract: A method for reading data from a memory module over a bi-directional bus is provided. The method initiates with issuing a read command. Then, a strobe signal is transitioned from a mid-rail state. In one embodiment, the strobe signal is transitioned to a logical low state. A read enable signal is then transitioned prior to a first falling edge of the strobe signal. The strobe signal represents an earliest availability for valid read data being available. The valid read data is read in response to the read enable signal transition. A microprocessor and a system wherein data is read over a bi-directional bus are included.