Abstract: Performance configurable controllers can include a variable performance storage device that has one or more communication channels for connection with a host-computing device and a plurality of memory devices within a memory array. The storage device may include controllers that provide access to separate memory devices within the memory array. The storage device can also have performance logic installed that can be configured to direct the controllers to operate at performance modes, each associated with a different level of performance. Each performance mode can be selectable by a host-computing device and can comprise one or more preconfigured control variables. In other embodiments, storage device performance can be configured to operate at various performance levels via direct control variable change requests sent from the host-computing system.

Abstract: Performance configurable controllers can include a variable performance storage device that has one or more communication channels for connection with a host-computing device and a plurality of memory devices within a memory array. The storage device may include controllers that provide access to separate memory devices within the memory array. The storage device can also have performance logic installed that can be configured to direct the controllers to operate at performance modes, each associated with a different level of performance. Each performance mode can be selectable by a host-computing device and can comprise one or more preconfigured control variables. In other embodiments, storage device performance can be configured to operate at various performance levels via direct control variable change requests sent from the host-computing system.

Abstract: A slave device includes a first port assigned an address resolution protocol (ARP) address, a plurality of second ports and corresponding endpoints, and a controller configured to receive first commands including the ARP address from the host through the first port, assign slave addresses to the endpoints based on the first commands to enable the second ports to communicate with the host, receive a second command including one of the slave addresses through a corresponding one of the second ports, perform an operation based on the second command to generate a result, and provide a result of the operation to the one second port.

Abstract: A slave device includes a first port assigned an address resolution protocol (ARP) address, a plurality of second ports and corresponding endpoints, and a controller configured to receive first commands including the ARP address from the host through the first port, assign slave addresses to the endpoints based on the first commands to enable the second ports to communicate with the host, receive a second command including one of the slave addresses through a corresponding one of the second ports, perform an operation based on the second command to generate a result, and provide a result of the operation to the one second port.

Abstract: A storage device includes at least one nonvolatile memory device, a host interface configured to communicate with a peripheral channel hub disposed external to the storage device, a sideband interface configured to receive a self-diagnostic command from a host disposed external to the storage device, and a self-diagnostic firmware configured to be driven in response to the self-diagnostic command to perform a self-diagnosis operation on the storage device.

Abstract: A storage device includes one or more nonvolatile memories, and a memory controller that controls the nonvolatile memories. The memory controller receives a new value from a host in compliance with a sideband interface protocol that is separate from a main interface protocol for transmitting normal data, such that an existing value of a condition parameter associated with an operation condition of the nonvolatile memories and the memory controller is changed into the new value. The new value is changed according to an aging level of the nonvolatile memories.

Abstract: A storage device includes at least one nonvolatile memory device, a host interface configured to communicate with a peripheral channel hub disposed external to the storage device, a sideband interface configured to receive a self-diagnostic command from a host disposed external to the storage device, and a self-diagnostic firmware configured to be driven in response to the self-diagnostic command to perform a self-diagnosis operation on the storage device.

Abstract: A control system for a power application is provided, including a control module and a configuration tool. The control module is in communication with the power application. The control module includes control logic for controlling the power application by a plurality of frame states. All of the frame states are executed within a period of time referred to as a frame rate. The control module includes control logic for allotting an adjustable amount of time for each of the frame states. The configuration tool is in communication with the control module. The configuration tool includes control logic for modifying the adjustable amount of time of each of the plurality of frame states without modifying the frame rate.

Abstract: A control system for a power application is provided, including a control module and a configuration tool. The control module is in communication with the power application. The control module includes control logic for controlling the power application by a plurality of frame states. All of the frame states are executed within a period of time referred to as a frame rate. The control module includes control logic for allotting an adjustable amount of time for each of the frame states. The configuration tool is in communication with the control module. The configuration tool includes control logic for modifying the adjustable amount of time of each of the plurality of frame states without modifying the frame rate.

Abstract: A brushless electric motor is disclosed. In an exemplary embodiment of the invention, the motor includes a permanent magnet rotor having a plurality of magnetic poles thereupon and a stator. The stator further includes a plurality of stacked laminations defining a plurality of slots therein, and a plurality of fractional-pitch phase windings disposed within the plurality of slots. The motor has a non-integer slots-per-pole ratio, and a magnitude of 5th and 7th harmonic components of a fundamental frequency component of the motor are less than 0.3% and 0.1% of a magnitude of the fundamental frequency component, respectively.

Abstract: A permanent magnet structure for use in brushless motors is disclosed. In an exemplary embodiment of the invention, the magnet structure includes a parallelogram shaped body. The body has an outer surface and an inner surface, with the outer surface and the inner surface being arcuate in shape.

Abstract: A permanent magnet structure for use in brushless motors is disclosed. In an exemplary embodiment of the invention, the magnet structure includes a parallelogram shaped body. The body has an outer surface and an inner surface, with the outer surface and the inner surface being arcuate in shape.

Abstract: A brushless electric motor is disclosed. In an exemplary embodiment of the invention, the motor includes a permanent magnet rotor having a plurality of magnetic poles thereupon and a stator. The stator further includes a plurality of stacked laminations defining a plurality of slots therein, and a plurality of fractional-pitch phase windings disposed within the plurality of slots. The motor has a non-integer slots-per-pole ratio, and a magnitude of 5th and 7th harmonic components of a fundamental frequency component of the motor are less than 0.3% and 0.1% of a magnitude of the fundamental frequency component, respectively.

Abstract: A brushless D.C. motor having a tolerance band that is used to retain the stator in the motor housing. The tolerance band has a plurality of waves formed along its length. The tolerance band is mounted within a housing groove, through which the stator is pressed. The tolerance band waves are compressed as the stator is pressed into motor housing. The compressed waves act as a radial spring to retain the stator in the housing with a minimal amount of radial force.

Abstract: A rotor assembly for a brushless motor is disclosed. In an exemplary embodiment of the invention, the rotor assembly includes a core having a central opening for insertion of a rotor shaft therein. A plurality of rotor magnets disposed upon a periphery of the core, wherein a space is defined between one of the plurality of rotor magnets and another of the plurality of rotor magnets. A portion of said core occupies said space, thereby defining a salient pole therewithin.

Abstract: A system for reducing torque ripple in an electric motor, comprising an electric motor having a stator and a rotor, a first set of N Hall sensors, a second set of N Hall sensors, a controller, and wherein said N Hall sensors in each said set of Hall sensors is spaced 360/N electrical degrees apart and said first and second sets of Hall sensors are spaced T electrical degrees apart, and wherein said controller is adapted to provide increased current during an overlap period detected by said Hall sensors.

Abstract: A method for determining a dimension in a motor is described. By applying Fourier analysis, a sequence of terms is obtained. Since the fifth harmonic is the most undesirable term, the minimization of the fifth harmonic term will make resultant waveform closer to sine wave. Based upon the above, a determination of an angle &dgr; is described, wherein the fifth harmonic term of the sequence of terms is minimized. An electric motor having a rotor and a set of slot on said rotor surface having a set of magnets with a width &dgr; along the circumference of said rotor surface is described. The width &dgr; is determined by a method that includes applying Fourier analysis thereby a sequence of terms is obtained. Since the fifth harmonic is the most undesirable term, the minimization of the fifth harmonic term will make resultant waveform closer to sine wave. Based upon the above, a determination of an angle &dgr; is described, wherein the fifth harmonic term of the sequence of terms is minimized.