Abstract: Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.

Abstract: Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.

Abstract: A configurable binary neural network (BNN) application-specific integrated circuit (ASIC) using a network of programmable threshold logic standard cells is provided. A new architecture is presented for a BNN that uses an optimal schedule for executing the operations of an arbitrary BNN. This architecture, also referred to herein as TULIP, is designed with the goal of maximizing energy efficiency per classification. At the top-level, TULIP consists of a collection of unique processing elements (TULIP-PEs) that are organized in a single instruction, multiple data (SIMD) fashion. Each TULIP-PE consists of a small network of binary neurons, and a small amount of local memory per neuron. Novel algorithms are presented herein for mapping arbitrary nodes of a BNN onto the TULIP-PEs. Comparison results show that TULIP is consistently 3× more energy-efficient than conventional designs, without any penalty in performance, area, or accuracy.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for an automated enterprise content management (ECM) migrator. One of the methods includes generating, by an enterprise content management process migration engine (ePME), a migration profile for migrating data from a first ECM system to a second ECM system. Determining content to extract associated with a process template from the first ECM system. Identifying at least one process and at least one activity associated with the at least one process associated with the process template. Determining at least one classification associated with the at least one process activity in the process template. Generating a database in the second ECM system storing each of the at least one process, the at least one activity, and the associated at least one classification from the template. Validating a successful transaction between the first ECM system and the second ECM system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for an automated enterprise content management (ECM) migrator. One of the methods includes generating, by an enterprise content management process migration engine (ePME), a migration profile for migrating data from a first ECM system to a second ECM system. Determining content to extract associated with a process template from the first ECM system. Identifying at least one process and at least one activity associated with the at least one process associated with the process template. Determining at least one classification associated with the at least one process activity in the process template. Generating a database in the second ECM system storing each of the at least one process, the at least one activity, and the associated at least one classification from the template. Validating a successful transaction between the first ECM system and the second ECM system.

Abstract: A CMOS driver circuit (20) has a high impedance driver (30) and a low impedance driver (36) connected to the near end of a transmission line (43). The output impedance of the high impedance driver (30) matches the characteristic impedance of the transmission line (43). As a digital signal from the CMOS driver circuit (20) transitions from one logic state to another, the low impedance driver (30) drives the transmission line (43) until a predetermined voltage before the signal reaches its steady state voltage. A sensing circuit (24) senses when the predetermined voltage is reached, and in response, provides a control signal to deactivate the low impedance driver (36). The high impedance driver (30) completes the signal transition. The high impedance driver (30) absorbs the reflected waves from the far end of the transmission line (43), reducing the effects of ringing, and increasing noise immunity.