Abstract: Embodiments of the present invention relate to an electronic device having programmable chip enable inputs in that each chip enable has a programmable assertion level, e.g., high or low. The device may be an integrated memory chip, e.g., SRAM device. On power up, a JTAG input port of the electronic device can be used to program a configuration register which contains bits for setting the assertion level of each chip enable input. The bits may be used to control respective multiplexers which select between a chip enable signal and its inverse. The chip enable signals may originate from a controller device. Regarding a memory device, the outputs of the multiplexers are coupled to chip enable signals of an integrated memory core.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to a reference impedance. The second circuit may be configured to operate in (i) a first mode in response to a first state of a second control signal and (ii) a second mode in response to a second state of the second control signal. When the second circuit is in the first mode, an output impedance of the second circuit may be adjusted in response to the one or more first control signals and the one or more first control signals may be presented at a first input/output of the second circuit. When the second circuit is in the second mode, the output impedance of the second circuit may be adjusted in response to one or more third control signals received at a second input/output of the second circuit.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to a reference impedance. The second circuit may be configured to operate in (i) a first mode in response to a first state of a second control signal and (ii) a second mode in response to a second state of the second control signal. When the second circuit is in the first mode, an output impedance of the second circuit may be adjusted in response to the one or more first control signals and the one or more first control signals may be presented at a first input/output of the second circuit. When the second circuit is in the second mode, the output impedance of the second circuit may be adjusted in response to one or more third control signals received at a second input/output of the second circuit.