Abstract: A circuit generally comprising a memory and a logic circuit. The memory may comprise (i) a first section configured to (a) read and write data and (b) have a first configurable size and (ii) a second section configured to (a) read and write data independently of the first section and (b) have a second configurable size. The logic circuit may be configured to control the first configurable size and the second configurable size.

Abstract: A dual port memory comprising a memory array, a first address circuit, a second address circuit, a timing circuit, a first data circuit and a second data circuit. The memory array may be configured to (i) write information to a first port or (ii) read information from a second port in response to (i) one or more first timing signals and (ii) one or more second timing signals. The first address circuit may be configured to present one or more first control signals in response to one or more first address signals. The second address circuit may be configured to present one or more second control signals in response to one or more second address signals. The timing circuit may be configured to present the one or more first timing signals and the one or more second timing signals in response to the one or more first control signals and the one or more second control signals. The first data circuit may be configured to read or write information from the first port of the memory array.

Abstract: A memory device (e.g., an SRAM) is configurable to be operated in an asynchronous or a synchronous mode in accordance with a value stored in a control register thereof. In addition to asynchronous and synchronous operating modes, additional features such burst mode operations, including asynchronous burst mode operations and/or synchronous burst mode operations (e.g., linear sequential and/or interleaved burst operations); the number of pipeline stages of an output path of the SRAM; and/or the number of data hold cycles for synchronous operation of the SRAM are configurable in accordance with additional values stored in the control register.