Abstract: A system for generating and maintaining lock files to inhibit conflicting requests for data files. A first process that accesses a data file generates a lock file to prohibit other processes from reading and/or writing that data file. Periodically the first process refreshes the lock file so that it shows a new modification time. A second process requesting access to the data file detect the lock file, stores the time of the attempted access, then waits a predetermined wait period and reads the lock file again. This is repeated, each time waiting for the wait period and again reading the lock file, until either (1) a predetermined time-out period passes without the first process refreshing the lock file, whereupon it is presumed that the process is defunct so the second process may access the data file; or (2) more than a maximum allowed access period of time has passed without the second process gaining access, i.e. the first process continues to refresh the lock file for greater than some predefined period.

Abstract: A RAM buffer is provided for managing the address inut lines of a RAM buffer to simulate the operation of two FIFO's therein. In addition, an apparatus is provided for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage transmit and receive FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Also disclosed is an apparatus for transmitting packets from said buffer organized into one or two linked lists. Further, an apparatus is provided for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor.

Abstract: A RAM buffer controller for managing the address input lines of a RAM buffer to simulate the operation of two FIFO's therein. Apparatus is included for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage "transmit and receive" FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Apparatus is also included for transmitting packets from said buffer organized into one or two linked lists. Further, apparatus is included for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant group of the checksum register. A group wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.

Abstract: There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus used 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock.